AM3354 DDR3 ddr_pll_config() issue in uboot

zhirong wu

Hi:

I use the a DDR3 chip MT41K128M16JT-125 in my board, now the CCS can initialize the EMIF and DDR3 TIMx, read and write DDR3 is correct through CCS; but when use uboot to initialize DDR3 through

ddr_pll_config(303)

config_am335_sk_ddr3()

the uboot write 0xa5a5a5a5 for test, then read the DDR3 at same address, all the return value is 0; if I delete ddr_pll_config(303) , then write and read test correctly sometimes, what I may be encountered? if not set the ddr_pll_config(303), the DDR3 is running which frequency?

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Wu,

Have you done everything as described in these links:

http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

0 zhirong wu over 12 years ago in reply to Biser Gatchev-XID

Intellectual 270 points

Thanks for your reply;

My board is refer to the TMDSSK3358 Board, the DDR_CLK and DDR_CLKn is connected with a 33ohm resistance and a 0.1uF capacitance to VDDS_DDR(0.75v) , I found that have a damper with this circuit after test the clk output with 100M,150M,200M. I have to remove the resistance, the DDR_CLK and DDR_CLKn is output 303MHZ correctly now and I can see the wave through the oscilloscope. The DDR3 timing parameters have be optimized according to documents of your list.

0 Biser Gatchev-XID over 12 years ago in reply to zhirong wu

TI__Guru**** 393215 points

Hi Wu,

DDR_CLK and DDR_CLKn have to be connected with 49.9Ohm 1% serial resistance and a 0.1uF capacitance to the DDR 1.5V supply, not to 0.75V. Also the Address/Control serial resistors to VTT have to be 51Ohm 1%. The 33Ohm values used on the SK are for this particular board design and stack-up, typical impedances on the DDR lines are 50Ohm.

0 zhirong wu over 12 years ago in reply to Biser Gatchev-XID

Intellectual 270 points

HI,

I use only one DDR3 chip on the board, but all the resistors is connected to VDDS_DDR(0.75v); If I try to remove all resistors that connect Address/Control/Clk to VDDS_DDR(0.75v) , it can working fine. Maybe this rework have other bad effect for the DDR3 transmission?

0 Biser Gatchev-XID over 12 years ago in reply to zhirong wu

TI__Guru**** 393215 points

Hi Wu,

Please take a careful look into the Starter Kit schematics. The CLK and CLKn resistors MUST be connected to the memory power rail (1.5V) through a 100nF capacitor. The other Address/Control signals must be connected to VTT, which is a 0.75V voltage sourced from a specific VTT regulator (U14 on Starter Kit).

0 zhirong wu over 12 years ago in reply to Biser Gatchev-XID

Intellectual 270 points

Hi Biser

Thanks very much!

I rework the board according to your advice again, it working fine now! BTW, the CLK and CLKn are all connected to 1.5v by my written errors above.

0 Viral Chavda over 12 years ago in reply to zhirong wu

Prodigy 160 points

I have done software leveling as per describe in wiki link. Now by register setting of DDR3 in GEL file, it is working fine at 303MHz using JTAG. I have modified all DDR3 registers in u-boot and all are same as GEL file. But still DDR3 is not working at 303MHz, however it is working fine at 200MHz with same register setting, I am unable to identify reason. Please help me to figure out the problem.

Regards

Viral Chavda.

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AM3354 DDR3 ddr_pll_config() issue in uboot