Hi Ti Folks,
Well to test this LTE20MHz 8xlink cpri test code.
/****************************************************************************\
* Copyright (C) 2009 Texas Instruments Incorporated. *
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*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <c6x.h>
#include <ti/csl/src/intc/csl_intc.h>
#include <sfp\BSLC667X_sfp.h>
#include <ti\csl\csl_pscAux.h>
#include <control/BSLC667X_control.h>
#include <dsp\uart\BSLC667X_uart.h>
#include "..\src\Aif2_config.h"
#define __VERSION__ "Ver 0.10"
/* Define queues for common FDQs */
#define MONO_TX_COMPLETE_Q 2000
#define MONO_RX_FDQ 2001
/* These are for the AIF test */
#define MONO_RX_Q 900
#define MONO_TX_Q 512
//Users should use 16 bytes aligned data for Aif2 and PktDMA test
#pragma DATA_SECTION(mono_region,".extData_sect")//use MSMC memory for test mode
#pragma DATA_ALIGN (mono_region, 16)
Uint8 mono_region[32 * 8848];//payload size is 8.8K bytes for Normal cyclic prefix 20 MHz LTE
Uint32 tmp[14];
/* Intc variable declarartion */
CSL_IntcObj intcObj;
CSL_IntcHandle hIntc;
CSL_IntcEventHandlerRecord EventHandler[8];
CSL_IntcGlobalEnableState state;
/* Global structures and variables */
CSL_Aif2Obj Aif2Obj;// Aif2 CSL object
CSL_Aif2Handle hAif2;// Aif2 handle
Bool ctrlArg; // Ctrl Argument;
CSL_Aif2Context Aif2Context;//Aif2 context
CSL_Aif2Param aif2Param;//AIF2 module specific parameters
CSL_Status status; // CSL status
CSL_Aif2Setup aif2Setup;//Aif2 HW setup
CSL_Aif2LinkSetup linkSetup;// Setup for links
CSL_Aif2GlobalSetup globalSetup;// global config for AIF2
CSL_Aif2CommonSetup commonSetup; // Setup for common params
CSL_Aif2SdCommonSetup SdCommonSetup;//SERDES common setup
CSL_Aif2PdCommonSetup PdCommonSetup;//PD common setup
CSL_Aif2PeCommonSetup PeCommonSetup;//PE common setup
CSL_Aif2IngrDbSetup IngrDbSetup;// Ingress data buffer setup
CSL_Aif2EgrDbSetup EgrDbSetup;// Egress data buffer setup
CSL_Aif2AdCommonSetup AdCommonSetup;// Aif2 DMA common setup
CSL_Aif2AtCommonSetup AtCommonSetup; // Aif2 Timer common setup
CSL_Aif2AtEventSetup AtEventSetup; // Aif2 Timer external and internal event setup
CSL_Aif2AtCountObj PhyTimerTc;// AT Phy Terminal Count setup
CSL_Aif2AtCountObj RadTimerTc;// AT Rad Terminal Count setup
CSL_Aif2AtCountObj PhyTimerInit;// AT Phy Init value setup
CSL_Aif2AtCountObj RadTimerInit;// AT Rad Init value setup
CSL_Aif2CommonLinkSetup ComLinkSetup; // Aif2 link common setup
CSL_Aif2SdLinkSetup SdLinkSetup; //SERDES link setup
CSL_Aif2RmLinkSetup RmLinkSetup; //RM link setup
CSL_Aif2TmLinkSetup TmLinkSetup; //TM link setup
CSL_Aif2PdLinkSetup PdLinkSetup; //PD link setup
CSL_Aif2PeLinkSetup PeLinkSetup; //PE link setup
CSL_Aif2RtLinkSetup RtLinkSetup; //RT link setup
CSL_Aif2AtLinkSetup AtLinkSetup; // Aif2 timer link setup (Pi, Delta, PE signal)
volatile unsigned int int4_result;
interrupt void int4_isr()
{
int i;
if (int4_result == 0)
{
for (i=0; i<14; i++)
push_queue(MONO_TX_Q, 1, 0, tmp[i]);
}
int4_result++;
}
char Uart_IsKey(void);
char Uart_GetKey(void);
int Uart_GetString(char *string);
int Uart_Printf (const char *fmt, ...);
char decCmd (char *s, int *addr, unsigned int *data, int *NumData);
void logo (void);
void Intc_config(void)
{
CSL_IntcParam vectId;
CSL_IntcContext context;
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
//! GEM0 Intc Configuration !//
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
/* Setup the global Interrupt */
context.numEvtEntries = 8;
context.eventhandlerRecord = EventHandler;
CSL_intcInit(&context);
/* Enable NMIs */
CSL_intcGlobalNmiEnable();
/* Enable Global Interrupts */
CSL_intcGlobalEnable(&state);
/* VectorID for the Global Edma Event */
vectId = CSL_INTC_VECTID_4;
/* Opening a handle for the Fsync->EDMA Interrupt Event */
hIntc = CSL_intcOpen(&intcObj,
AIF2_EVENT2_INTSEL_MAP, // Event2
&vectId,
NULL);
//Hook the ISRs
CSL_intcHookIsr(vectId, &int4_isr);
// Clear the Interrupt
CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTCLEAR, NULL);
//Enable the Event & the interrupt
CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTENABLE, NULL);
}
void MNavigator_config(void)
{
Uint32 flow_a;
Uint32 flow_d;
Uint16 idx;
MNAV_MonolithicPacketDescriptor *mono_pkt;
/* Setup Memory Region 0 for 32 8848B Monolithic descriptors. Our
* Mono descriptors will be 12 bytes plus 4 bytes protocol specific field, plus
* 8832(8768) bytes of payload(symbol). so the total size is 8848 and it is dividable by 16
* 32 descriptors. (dead space is possible) */
set_memory_region(0, (Uint32) mono_region, 0, 0x02280000);
/*****************************************************************
* Configure Linking RAM 0 for the descriptor regions.
*/
set_link_ram(0, QM_LRAM_REGION, 0x3fff); //internal link ram
/* Initialize descriptor regions to zero */
memset(mono_region, 0, 64 * 8848);
/* Push 7 Monolithic packets into Tx Completion Queue */
for (idx = 0; idx < 14; idx ++)
{
mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 8848));
mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
mono_pkt->data_offset = 16;
mono_pkt->pkt_return_qmgr = 0;
mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q;
push_queue(MONO_TX_COMPLETE_Q, 1, 0, (Uint32)(mono_pkt));
}
/* Push 7 Monolithic packets to Rx FDQ */
for (idx = 16; idx < 16+14; idx ++)
{
mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 8848));
mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
mono_pkt->data_offset = 16;
push_queue(MONO_RX_FDQ, 1, 0, (Uint32)(mono_pkt));
}
/*****************************************************************
* Configure Rx channel flows
*/
/* Note that when LOOPBACK_MODE is enabled, the PKTDMA will force
* force the flow ID value in the Tx Streaming I/F to be equal to
* the channel number. (normally, the Tx flow ID is set to 0xff).
* This is a simulator special testing feature. */
//Create flow configuration 0 for the Monolithic packets
flow_a = 0x28100000 | MONO_RX_Q;
flow_d = MONO_RX_FDQ << 16;
config_rx_flow(AIF_PKTDMA_RX_FLOW_REGION, 0,
flow_a, 0, 0, flow_d, 0, 0, 0, 0);
/*****************************************************************
* Enable Tx and Rx channels.
*/
enable_disable_loopback(0);//disable PKTDMA loopback for normal data transfer
config_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 0, 0x01000000); //set AIF_MONO_MODE to 1 and set PS filter to zero
enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 0, 0x80000000);
enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, 0, 0x80000000);
}
void Aif2_MNAV_Cpri_config(CSL_Aif2LinkIndex link)
{
int i;
/************ Initialize Aif2 structures to avoid unwanted configuration ************************************************/
memset(&globalSetup, 0, sizeof(globalSetup));
memset(&linkSetup, 0, sizeof(linkSetup));
memset(&commonSetup, 0, sizeof(commonSetup));
memset(&SdCommonSetup, 0, sizeof(SdCommonSetup));
memset(&PdCommonSetup, 0, sizeof(PdCommonSetup));
memset(&PeCommonSetup, 0, sizeof(PeCommonSetup));
memset(&IngrDbSetup, 0, sizeof(IngrDbSetup));
memset(&EgrDbSetup, 0, sizeof(EgrDbSetup));
memset(&AdCommonSetup, 0, sizeof(AdCommonSetup));
memset(&AtCommonSetup, 0, sizeof(AtCommonSetup));
memset(&AtEventSetup, 0, sizeof(AtEventSetup));
memset(&PhyTimerInit, 0, sizeof(PhyTimerInit));
memset(&RadTimerInit, 0, sizeof(RadTimerInit));
memset(&PhyTimerTc, 0, sizeof(PhyTimerTc));
memset(&RadTimerTc, 0, sizeof(RadTimerTc));
memset(&ComLinkSetup, 0, sizeof(ComLinkSetup));
memset(&SdLinkSetup, 0, sizeof(SdLinkSetup));
memset(&RmLinkSetup, 0, sizeof(RmLinkSetup));
memset(&TmLinkSetup, 0, sizeof(TmLinkSetup));
memset(&PdLinkSetup, 0, sizeof(PdLinkSetup));
memset(&PeLinkSetup, 0, sizeof(PeLinkSetup));
memset(&RtLinkSetup, 0, sizeof(RtLinkSetup));
memset(&AtLinkSetup, 0, sizeof(AtLinkSetup));
// Initialize CSL library, this step is required
CSL_aif2Init(&Aif2Context);
// Open Aif2 and get handle
hAif2 = CSL_aif2Open(&Aif2Obj, CSL_AIF, &aif2Param, &status);
if ((hAif2 == NULL) || (status != CSL_SOK))
{
printf ("\nError opening CSL_AIF2");
exit(1);
}
/************** populating AIF2 major setup structures ***************************************************/
aif2Setup.globalSetup = &globalSetup;
aif2Setup.commonSetup = &commonSetup;
aif2Setup.linkSetup[link] = &linkSetup;//assign only one link setup for link
// populate global config fields
globalSetup.ActiveLink[link] = TRUE;//Activate link for this test
globalSetup.frameMode = CSL_AIF2_FRAME_MODE_NORMAL;
//populate common config fields
commonSetup.pSdCommonSetup = &SdCommonSetup;
commonSetup.pPdCommonSetup = &PdCommonSetup;
commonSetup.pPeCommonSetup = &PeCommonSetup;
commonSetup.pIngrDbSetup = &IngrDbSetup;
commonSetup.pEgrDbSetup = &EgrDbSetup;
commonSetup.pAdCommonSetup = &AdCommonSetup;
commonSetup.pAtCommonSetup = &AtCommonSetup;
commonSetup.pAtEventSetup = &AtEventSetup;
/****Link Setup (Do this setup repeatedly with different link setup structure if user wants to use multiple links) ***/
//populate link config fields for link
linkSetup.linkIndex = link;
linkSetup.pComLinkSetup = &ComLinkSetup;
linkSetup.pSdLinkSetup = &SdLinkSetup;
linkSetup.pRmLinkSetup = &RmLinkSetup;
linkSetup.pTmLinkSetup = &TmLinkSetup;
linkSetup.pPdLinkSetup = &PdLinkSetup;
linkSetup.pPeLinkSetup = &PeLinkSetup;
linkSetup.pRtLinkSetup = &RtLinkSetup;
linkSetup.pAtLinkSetup = &AtLinkSetup;
//Link Common setup
ComLinkSetup.linkProtocol = CSL_AIF2_LINK_PROTOCOL_CPRI;
ComLinkSetup.linkRate = CSL_AIF2_LINK_RATE_8x;
ComLinkSetup.IngrDataWidth = CSL_AIF2_DATA_WIDTH_15_BIT;
ComLinkSetup.EgrDataWidth = CSL_AIF2_DATA_WIDTH_15_BIT;
//SD link setup
SdLinkSetup.rxAlign = CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE;
SdLinkSetup.rxLos = CSL_AIF2_SD_RX_LOS_ENABLE;
SdLinkSetup.rxCdrAlgorithm = CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_17;
SdLinkSetup.rxInvertPolarity = CSL_AIF2_SD_RX_NORMAL_POLARITY;
SdLinkSetup.rxTermination = CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 ;//for AC coupled application
SdLinkSetup.rxEqualizerConfig = CSL_AIF2_SD_RX_EQ_ADAPTIVE;//Equalizer On
SdLinkSetup.bRxEqHold = FALSE;//fixed value
SdLinkSetup.bRxOffsetComp = TRUE;//fixed value
SdLinkSetup.bEnableTxSyncMater = TRUE; //fixed value
SdLinkSetup.txInvertPolarity = CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY;
SdLinkSetup.txOutputSwing = CSL_AIF2_SD_TX_OUTPUT_SWING_14;
SdLinkSetup.txPrecursorTapWeight = CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2;// -5%
SdLinkSetup.txPostcursorTapWeight = CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24;// -20%
SdLinkSetup.bTxFirFilterUpdate = TRUE;//FIR filter update on
//TM link setup
TmLinkSetup.bEnableTmLink = TRUE;
TmLinkSetup.bEnableRmLos = FALSE;
TmLinkSetup.SeedValue = 0x1;
TmLinkSetup.bEnableScrambler = FALSE;
TmLinkSetup.pCpriTmSetup.L1InbandEn = 0;//disable 9 bits mask
TmLinkSetup.pCpriTmSetup.RmLinkLosError = link;//select link as source RM link
TmLinkSetup.pCpriTmSetup.RmLinkLofError = link;//select link as source RM link
TmLinkSetup.pCpriTmSetup.RmLinkLosRx = link;//select link as source RM link
TmLinkSetup.pCpriTmSetup.RmLinkLofRx = link;//select link as source RM link
TmLinkSetup.pCpriTmSetup.RmLinkRaiRx = link;//select link as source RM link
TmLinkSetup.pCpriTmSetup.TxStartup = 0;
TmLinkSetup.pCpriTmSetup.TxPointerP = 20;
TmLinkSetup.pCpriTmSetup.TxProtocolVer = 1;
//RM link setup
RmLinkSetup.bEnableRmLink = TRUE;
RmLinkSetup.RmFifoThold = CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY;
RmLinkSetup.RmErrorSuppress = CSL_AIF2_RM_ERROR_ALLOW;
RmLinkSetup.bEnableSdAutoAlign = FALSE;
RmLinkSetup.bEnableScrambler = FALSE;
RmLinkSetup.bEnableLcvUnsync = FALSE;
RmLinkSetup.bEnableLcvControl = FALSE;
RmLinkSetup.bEnableWatchDog = FALSE;
RmLinkSetup.WatchDogWrap = 0xFF;//set watch dog wrap value
RmLinkSetup.bEnableClockQuality = FALSE;
RmLinkSetup.ClockMonitorWrap = 0;//disabled
RmLinkSetup.losDetThreshold = RM_LOS_DET_THOLD;
RmLinkSetup.SyncThreshold = RM_SYNC_THOLD;
RmLinkSetup.FrameSyncThreshold = RM_SYNC_THOLD;
RmLinkSetup.UnsyncThreshold = RM_UNSYNC_THOLD;
RmLinkSetup.FrameUnsyncThreshold = RM_UNSYNC_THOLD;
//RT link setup
RtLinkSetup.CiSelect = link;
RtLinkSetup.bEnableEmptyMsg = TRUE;
RtLinkSetup.RtConfig = CSL_AIF2_RT_MODE_TRANSMIT;// takes PE input only
//PD link setup
PdLinkSetup.bEnablePdLink = TRUE;
PdLinkSetup.CpriEnetStrip = 0;//disable ethernet strip for control channel
PdLinkSetup.Crc8Poly = CRC8_POLY;
PdLinkSetup.Crc8Seed = CRC8_SEED;
PdLinkSetup.CpriCwNullDelimitor = 0xFB;//K 27.7 charactor
PdLinkSetup.CpriCwPktDelimitor[0] = CSL_AIF2_CW_DELIM_NULLDELM;//4
PdLinkSetup.PdCpriCrcType[0] = CSL_AIF2_CRC_16BIT;
PdLinkSetup.bEnableCpriCrc[0] = TRUE;//enable CPRI CRC for control channel 0
PdLinkSetup.PdPackDmaCh[0] = 124;//Set DB channel 124 as a dma ch for control channel 0
PdLinkSetup.bEnablePack[0] = TRUE;//enable CPRI control channel 0 packing
PdLinkSetup.PdCpriDualBitMap.DbmX = 1;// set X-1
PdLinkSetup.PdCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample
PdLinkSetup.PdCpriDualBitMap.Dbm1Mult = 0;//set n-1
PdLinkSetup.PdCpriDualBitMap.Dbm1Size = 0;//set n-1
PdLinkSetup.PdCpriDualBitMap.Dbm1Map[0] = 0x0;
PdLinkSetup.PdCpriDualBitMap.Dbm2Size = 0;
PdLinkSetup.PdCpriDualBitMap.Dbm2Map[0] = 0x0;
PdLinkSetup.CpriDmaCh[0]= 0; //match DbmX channel 0 to DB channel 0
PdLinkSetup.bEnableCpriX[0]= TRUE; //enable CPRI X channel 0
PdLinkSetup.bEnableCpriPkt[0]= FALSE;//use AxC data for X channel 0
PdLinkSetup.Cpri8WordOffset[0]= 0;//Word level CPRI data offset for X channel 0
for(i=0;i<256;i++)//cpri cw lut setup
{
PdLinkSetup.CpriCwChannel[i]= 0; //set cw channel num to pack 0
PdLinkSetup.bEnableCpriCw[i]= TRUE; //enable CPRI CW sub channel
}
//PE link setup
PeLinkSetup.bEnablePeLink = TRUE;
PeLinkSetup.PeCppiDioSel = CSL_AIF2_CPPI;
PeLinkSetup.TddAxc = FALSE;
PeLinkSetup.PeDelay = DB_PE_DELAY_CPRI;//0 sys_clks delay between DB and PE
PeLinkSetup.Crc8Poly = CRC8_POLY;
PeLinkSetup.Crc8Seed = CRC8_SEED;
PeLinkSetup.PeCpriDualBitMap.DbmX = 1;//set X-1
PeLinkSetup.PeCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample
PeLinkSetup.PeCpriDualBitMap.Dbm1Mult = 0;//set n-1
PeLinkSetup.PeCpriDualBitMap.Dbm1Size = 0;//set n-1
PeLinkSetup.PeCpriDualBitMap.Dbm1Map[0] = 0x0;
PeLinkSetup.PeCpriDualBitMap.Dbm2Size = 0;
PeLinkSetup.PeCpriDualBitMap.Dbm2Map[0] = 0x0;
PeLinkSetup.CpriAxCPack = CSL_AIF2_CPRI_15BIT_SAMPLE;
PeLinkSetup.CpriCwNullDelimitor = 0xFB;//K 27.7 character
PeLinkSetup.CpriCwPktDelimitor[0] = CSL_AIF2_CW_DELIM_NULLDELM;
PeLinkSetup.PePackDmaCh[0] = 124;
PeLinkSetup.bEnablePack[0] = TRUE;
for(i=0;i<256;i++)//cpri cw lut setup
{
PeLinkSetup.CpriCwChannel[i]= 0; //set cw channel num to pack 0
PeLinkSetup.bEnableCpriCw[i]= TRUE; //enable CPRI CW sub channel
}
//AT link setup
AtLinkSetup.PE1Offset = 300;
AtLinkSetup.PE2Offset = 310;
AtLinkSetup.DeltaOffset = 380;
AtLinkSetup.PiMin = 380;
AtLinkSetup.PiMax = 400;
AtLinkSetup.IsNegativeDelta = FALSE;//positive delta
/************** Common Setup ********************************************************************************/
//SD common setup
SdCommonSetup.bEnablePllB8 = TRUE;
SdCommonSetup.CLKBYP_B8 = CSL_AIF2_PLL_CLOCK_NO_BYPASS;
SdCommonSetup.LB_B8 = CSL_AIF2_PLL_LOOP_BAND_MID;//High BW is also fine
SdCommonSetup.VoltRangeB8 = CSL_AIF2_PLL_VOLTAGE_LOW;//fixed factor
SdCommonSetup.SleepPllB8 = CSL_AIF2_PLL_AWAKE;
SdCommonSetup.pllMpyFactorB8 = CSL_AIF2_PLL_MUL_FACTOR_20X;//for CPRI when reference clock is 122.88 Mhz
SdCommonSetup.SysClockSelect = CSL_AIF2_SD_BYTECLOCK_FROM_B8;
SdCommonSetup.DisableLinkClock[0] = FALSE;//enable LINK0 clock
SdCommonSetup.DisableLinkClock[1] = FALSE;//enable LINK1 clock
SdCommonSetup.DisableLinkClock[2] = FALSE;//enable LINK2 clock
SdCommonSetup.DisableLinkClock[3] = TRUE;//disable LINK3 clock
SdCommonSetup.DisableLinkClock[4] = TRUE;//disable LINK4 clock
SdCommonSetup.DisableLinkClock[5] = TRUE;//disable LINK5 clock
//PD common setup
PdCommonSetup.PdCppiDioSel = CSL_AIF2_CPPI;//AxC data uses CPPI for DMA machine
PdCommonSetup.AxCOffsetWin = AXC_OFFSET_WIN;//AxC offset window
PdCommonSetup.PdRadtTC = 2457599;//Radio frame size for CPRI
PdCommonSetup.PdFrameTC[0].FrameIndexSc = 0;//start index
PdCommonSetup.PdFrameTC[0].FrameIndexTc = 6;//teminal index
PdCommonSetup.PdFrameTC[0].FrameSymbolTc = 139;//140 noramal cyclic prefix symbols in one rad frame.
PdCommonSetup.PdChConfig[0].bChannelEn = TRUE;//Channel enable for channel 0
PdCommonSetup.PdChConfig[0].DataFormat = CSL_AIF2_LINK_DATA_TYPE_NORMAL;//Data format for channel 0
PdCommonSetup.AxCOffset[0] = 0;//this is the number of QW level data to skip
PdCommonSetup.PdChConfig1[0].DataFormat = CSL_AIF2_GSM_DATA_OTHER;//Non GSM data
PdCommonSetup.PdChConfig1[0].FrameCounter = 0;//CPRI framing counter group number for channel 0
PdCommonSetup.PdChConfig1[0].TddEnable = 0xFFFF;//PD TDD, enables all symbols(FDD) for channel 0
PdCommonSetup.TddEnable1[0] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.TddEnable2[0] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.TddEnable3[0] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.TddEnable4[0] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.PdFrameMsgTc[0] = 551;//OBSAI frame message terminal count for first normal cyclic prefix symbol
for(i=1;i<7;i++)
PdCommonSetup.PdFrameMsgTc[i] = 547;//OBSAI frame message terminal count for ohter 6 normal cyclic prefix LTE symbols
//PE common setup
PeCommonSetup.PeTokenPhase = 0;//Phase alignment for scheduling DMA normally set to zero
PeCommonSetup.EnetHeaderSelect = 1;
PeCommonSetup.PeFrameTC[0].FrameIndexSc = 0;//start index
PeCommonSetup.PeFrameTC[0].FrameIndexTc = 6;//teminal index
PeCommonSetup.PeFrameTC[0].FrameSymbolTc = 139;//140 normal cyclic prefix symbols in one rad frame.
PeCommonSetup.bEnableCh[0] = TRUE;//Enable PE channel for channel 0
PeCommonSetup.PeDmaCh0[0].bCrcEn = FALSE;//disable CRC for channel 0
PeCommonSetup.PeDmaCh0[0].FrameTC = 0;//use framing terminal count 0 for channel 0
PeCommonSetup.PeDmaCh0[0].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option for channel 0
PeCommonSetup.PeDmaCh0[0].CrcType = CSL_AIF2_CRC_8BIT;//CRC type for channel 0
PeCommonSetup.PeDmaCh0[0].isEthernet = FALSE;//AxC data
PeCommonSetup.PeDmaCh0[0].CrcObsaiHeader = FALSE;
PeCommonSetup.PeInFifo[0].MFifoWmark = 3;//Message FIFO water mard for channel 0
PeCommonSetup.PeInFifo[0].MFifoFullLevel = 5;//Message FIFO full level for channel 0
PeCommonSetup.PeInFifo[0].SyncSymbol = 0;
PeCommonSetup.PeAxcOffset[0] = 310;// same to PE2 offset
PeCommonSetup.PeFrameMsgTc[0] = 2207;//OBSAI frame message terminal count for first normal cyclic prefix symbol
for(i=1;i<7;i++)
PeCommonSetup.PeFrameMsgTc[i] = 2191;//OBSAI frame message terminal count for ohter 6 normal cyclic prefix LTE symbols
//PE Channel LUT setup and link routing selection (ChIndex number is matched with link number)
switch(link)
{
case CSL_AIF2_LINK_0:
PeCommonSetup.ChIndex0[0] = 0; //channel 0 for link 0
PeCommonSetup.bEnableChIndex0[0] = TRUE;//Route egress channel 0 to dedicated CPRI link
PeCommonSetup.CpriPktEn0[0] = FALSE; //use channel 0 for AxC
break;
case CSL_AIF2_LINK_1:
PeCommonSetup.ChIndex1[0] = 0; //channel 0 for link 1
PeCommonSetup.bEnableChIndex1[0] = TRUE;//Route egress channel 0 to dedicated CPRI link
PeCommonSetup.CpriPktEn1[0] = FALSE; //use channel 0 for AxC
break;
case CSL_AIF2_LINK_2:
PeCommonSetup.ChIndex2[0] = 0; //channel 0 for link 2
PeCommonSetup.bEnableChIndex2[0] = TRUE;//Route egress channel 0 to dedicated CPRI link
PeCommonSetup.CpriPktEn2[0] = FALSE; //use channel 0 for AxC
break;
default:
printf("Link %d is not connected on this card\n", link);
}
//Ingress DB setup
IngrDbSetup.bEnableIngrDb = TRUE; //Enable Ingress DB
IngrDbSetup.bEnableChannel[0] = TRUE; //Enable Ingress DB channel 0
IngrDbSetup.IngrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0; //Set DB FIFO base address for channel 0
IngrDbSetup.IngrDbChannel[0].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW64; //Set DB FIFO depth for channel 0 to 64 QW(Quad word)
IngrDbSetup.IngrDbChannel[0].DataSwap = CSL_AIF2_DB_WORD_SWAP; //for DL
IngrDbSetup.IngrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
IngrDbSetup.IngrDbChannel[0].bEnablePsData = TRUE; //Enable 4 bytes PS data
IngrDbSetup.IngrDbChannel[0].PacketType = 0; //User data
//Egress DB setup
EgrDbSetup.bEnableEgrDb = TRUE; //Enable Ingress DB
EgrDbSetup.PmControl = CSL_AIF2_DB_AXC_TOKEN_FIFO;//to enhance CPRI performance
EgrDbSetup.bEnableChannel[0] = TRUE; //Enable Egress DB channel 0
EgrDbSetup.EgrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0; //Set DB FIFO base address for channel 0
EgrDbSetup.EgrDbChannel[0].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW64; //Set DB FIFO depth for channel 0 to 32 QW
EgrDbSetup.EgrDbChannel[0].DataSwap = CSL_AIF2_DB_WORD_SWAP; //for DL
EgrDbSetup.EgrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
//AD Common setup
AdCommonSetup.IngrGlobalEnable = TRUE;
AdCommonSetup.EgrGlobalEnable = TRUE;
AdCommonSetup.FailMode = CSL_AIF2_AD_DROP;//drop fail packet
AdCommonSetup.IngrPriority = CSL_AIF2_AD_PKT_PRI;
AdCommonSetup.EgrPriority = CSL_AIF2_AD_AXC_PRI;
AdCommonSetup.Tx_QueNum = AIF2_BASE_TX_QUE_NUM;//base egress queue number setup to 512
//AT Common setup
AtCommonSetup.PhySyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Phy timer trigger
AtCommonSetup.RadSyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Rad timer trigger
AtCommonSetup.SyncMode = CSL_AIF2_NON_RP1_MODE;
AtCommonSetup.AutoResyncMode = CSL_AIF2_AUTO_RESYNC_MODE;
AtCommonSetup.CrcMode = CSL_AIF2_AT_CRC_DONT_USE;//Do not use RP1 CRC in this test
AtCommonSetup.PhytCompValue = 0;
AtCommonSetup.AtInit.pPhyTimerInit = &PhyTimerInit;
AtCommonSetup.AtInit.pRadTimerInit = &RadTimerInit;
PhyTimerInit.ClockNum = 0;
PhyTimerInit.FrameLsbNum = 0;
PhyTimerInit.FrameMsbNum = 0;
RadTimerInit.ClockNum = 0;
RadTimerInit.SymbolNum = 0;
RadTimerInit.FrameLsbNum = 0;
RadTimerInit.FrameMsbNum = 0;
AtCommonSetup.AtTerminalCount.pPhyTimerTc = &PhyTimerTc;
AtCommonSetup.AtTerminalCount.pRadTimerTc = &RadTimerTc;
PhyTimerTc.FrameLsbNum = FRAME_COUNT_TC_PHY_TIMER;//set phy Frame TC to 4095
PhyTimerTc.ClockNum = CLOCK_COUNT_TC_PHY_TIMER_CPRI; //set phy clock TC for CPRI
RadTimerTc.FrameLsbNum = FRAME_COUNT_TC_LTE_FDD;//set LTE Frame TC to 4095
RadTimerTc.SymbolNum = SYMBOL_COUNT_TC_LTE_FDD; //set LTE Symbol TC to 9 (sub frame time)
RadTimerTc.LutIndexNum = 0; //set LTE lut index TC to zero
AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = CLOCK_COUNT_TC_LTE_FDD_CPRI;//set LTE Clock count TC forCPRI
//AT Event setup (Event 2)
AtEventSetup.AtRadEvent[2].EventSelect = CSL_AIF2_EVENT_2;//Select Event 2
AtEventSetup.AtRadEvent[2].EventOffset = 614399; //offset for inserting packet in frame at third frame time
AtEventSetup.AtRadEvent[2].EvtStrobeSel = CSL_AIF2_RADT_FRAME;
AtEventSetup.AtRadEvent[2].EventModulo = 2457599;//LTE frame time
AtEventSetup.AtRadEvent[2].EventMaskLsb = 0xFFFFFFFF;
AtEventSetup.AtRadEvent[2].EventMaskMsb = 0xFFFFFFFF;
AtEventSetup.bEnableRadEvent[2] = TRUE;//Enable Event 2
/****** Do AIF2 HW setup (set all MMRs above) **********************************************************************/
CSL_aif2HwSetup(hAif2, &aif2Setup);
ctrlArg = TRUE;
hAif2->arg_link = link;//Select link num
//Enable Serdes loopback for link
//CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg);
//Enable Tx/Rx of link
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);
for(i=0;i<100;i++)asm (" NOP 9 ");//insert time delay for aif2 configuration complete
//AT Arm timer
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_ARM_TIMER, (void *)&ctrlArg);
//Trigger the SW debug frame sync
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DEBUG_SYNC, (void *)&ctrlArg);
}
BSLC667X_ErrorCode BSLC667X_AIF_init()
{
BSLC667X_ErrorCode Err;
/* Default configuration will only be used if FRU read fails from DSP */
BSLC667X_Libconfig_s LibConfig = {BSLC667X_CPU_CLK_FREQ_1200_MHZ,BSLC667X_BOARD_CFG_DEFAULT_AMC2C6670,TRUE,TRUE};
/* Initialise PLLC, DDR2 and BSLC667X Library */
Err = BSLC667X_Initialise(&LibConfig);
if (Err)
{
printf("BSLC667X_Initialise() failed!!, ErrorCode = 0x%x\n",Err);
return 1;
}
/* Initialise SFP module */
if(BSLC667X_SfpInitialise(NULL))
{
printf("BSLC667X_SfpInitialise() failed!!");
return 1;
}
printf("SFP Interface Initialised\n");
Err = BSLC667X_SfpTxEnable(BSLC667X_SFP0_CHANNEL);
Err |= BSLC667X_SfpTxEnable(BSLC667X_SFP1_CHANNEL);
Err |= BSLC667X_SfpTxEnable(BSLC667X_SFP2_CHANNEL);
if(Err)
{
printf("BSLC667XSfpTxEnable failed, Err=0x%x\n", Err);
}
/* Turn on the Hyperlink power domain */
if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_AI) != PSC_PDSTATE_ON) {
/* Enable the domain */
CSL_PSC_enablePowerDomain (CSL_PSC_PD_AI);
/* Enable MDCTL */
CSL_PSC_setModuleNextState (CSL_PSC_LPSC_AI, PSC_MODSTATE_ENABLE);
/* Apply the domain */
CSL_PSC_startStateTransition (CSL_PSC_PD_AI);
/* Wait for it to finish */
while (! CSL_PSC_isStateTransitionDone (CSL_PSC_PD_AI));
} else {
printf ("Power domain is already enabled. You probably re-ran without device reset (which is OK)\n");
}
return 0;
}
void test_lte_cpri(CSL_Aif2LinkIndex link)
{
Uint32 monoRxCount;
Uint16 testpass;
Uint32 *temp;
Uint32 idx, idx2, value;
MNAV_MonolithicPacketDescriptor *mono_pkt;
//printf("Beginning AIF2 CPRI LTE test:\n\n");
//for(idx=0;idx<10000;idx++)asm (" NOP 9 ");//insert time delay for printf operation
int4_result = 0;
Intc_config();
MNavigator_config();//multicore navigator configuration for LTE
for(idx =0; idx < 14; idx++){ //push 7 packets into Tx queue for test
tmp[idx] = pop_queue(MONO_TX_COMPLETE_Q);
tmp[idx] &= 0xFFFFFFF0;//set DESC_SIZE field to zero
mono_pkt = (MNAV_MonolithicPacketDescriptor *)tmp[idx];
//Create Mono packet (initialize non-zero fields)
mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
mono_pkt->data_offset = MNAV_MONO_PACKET_SIZE + 4;//16
if((idx%7) == 0) mono_pkt->packet_length = 8832;//first symbol
else mono_pkt->packet_length = 8768;//other six symbols
mono_pkt->ps_flags = 1;
mono_pkt->epib = 0;
mono_pkt->psv_word_count = 1; // 4 byte PS field length
mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q;
mono_pkt->src_tag_lo = 0; //copied to .flo_idx of streaming i/f
temp = (Uint32 *)(tmp[idx] + 16);
if((idx%7) == 0)
{
for (idx2 = 0; idx2 < 2208; idx2 ++)
temp[idx2] = idx2; //payload data setup(first symbol)
}
else
{
for (idx2 = 0; idx2 < 2192; idx2 ++)
temp[idx2] = idx2; //payload data setup(other six symbols)
}
//Create PS data
temp = (Uint32 *)(tmp[idx] + MNAV_MONO_PACKET_SIZE);
temp[0] = (Uint32)(0x00008000 + (idx << 7));//add symbol number into PS field
tmp[idx] |= 0x00000003;//set DESC_SIZE to 3 for AIF2 mono mode
//Tx queue push will be done in ISR
}
Aif2_MNAV_Cpri_config(link);//Aif2 configuration for M Navigator mode
/*****************************************************************
* Enable AIF and wait for completion.
*/
while(1)
{
asm (" NOP 9 ");
asm (" NOP 9 ");
if(int4_result == 4)//Wait three LTE frame time
{
//AT disable all events and halt timer
ctrlArg = TRUE;
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_HALT_TIMER, (void *)&ctrlArg);
ctrlArg = FALSE;//disable AD scheduler and Rx, Tx Link
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);
CSL_aif2Reset(hAif2);//reset all aif2 modules
break;
}
}
monoRxCount = 0; // descriptor count for monolithic RX queue
while (monoRxCount == 0)
{
// Get current descriptor count for monolithic RX queue
monoRxCount = get_descriptor_count(MONO_RX_Q);
if (monoRxCount > 0)
printf(" Number of monolithic packets received in RX queue: %d\n", monoRxCount);
if (Uart_GetKey() == 0x1b) break;
}
/*****************************************************************
* Compare the data in the destination buffers.
*/
/* Compare the Monolithic packet data */
testpass = 0;
for (idx = 0; idx < monoRxCount; idx ++)
{
tmp[idx] = pop_queue(MONO_RX_Q);
tmp[idx] &= 0xFFFFFFF0;// clean DESC_SIZE field
temp = (Uint32 *)tmp[idx];
temp += 4; //skip pkt header and PS field (16 bytes)
if((idx%7) == 0)
{
for (idx2 = 0; idx2 < 2208; idx2 ++)
{
if (temp[idx2] != idx2)
testpass++;
}
}
else {
for (idx2 = 0; idx2 < 2192; idx2 ++)
{
if (temp[idx2] != idx2)
testpass++;
}
}
push_queue(MONO_RX_FDQ, 1, 0, tmp[idx]);
}
/* read the descriptor counts of the Monolithic queues. */
value = get_descriptor_count(MONO_TX_Q);
if (value != 0) printf(" Test b1) Monolithic Packet Tx Descriptor Counts:%d FAIL\n",value);
else printf(" Test b1) Monolithic Packet Tx Descriptor Counts:%d PASS\n",value);
if (value != 0) testpass++;
value = get_descriptor_count(MONO_TX_COMPLETE_Q);
if (value != 14) printf(" Test b2) Monolithic Packet Tx Complete Descriptor Counts:%d FAIL\n",value);
else printf(" Test b2) Monolithic Packet Tx Complete Descriptor Counts:%d PASS\n",value);
if (value != 14) testpass++;
value = get_descriptor_count(MONO_RX_Q);
if (value != 0) printf(" Test b3) Monolithic Packet Rx Descriptor Counts:%d FAIL\n",value);
else printf(" Test b3) Monolithic Packet Rx Descriptor Counts:%d PASS\n",value);
if (value != 0) testpass++;
value = get_descriptor_count(MONO_RX_FDQ);
if (value != 14) printf(" Test b4) Monolithic Packet Rx Free Descriptor Counts:%d FAIL\n",value);
else printf(" Test b4) Monolithic Packet Rx Free Descriptor Counts:%d PASS\n",value);
if (value != 14) testpass++;
if (testpass == 0) printf(" Test a) Monolithic Packet Data Send/Recv: PASS\n");
else printf(" Test a) Monolithic Packet Data Send/Recv: FAIL\n");
if (testpass == 0) Uart_Printf("Link%d Data Send/Recv: PASS\r\n", link);
else Uart_Printf("Link%d Data Send/Recv: FAIL %d\r\n", link, testpass);
printf("\nEnding AIF2 CPRI LTE test\n");
}
void main(void)
{
char SelRW, command[128];
int i, addr, NumData, addr_offset=0x00000000;
unsigned int data[32], tmp;
int Err;
BSLC667X_AIF_init();
/* Initialise UART module */
if (Err = BSLC667X_UartInitialise(NULL))
printf("BSLC667X_UartInitialise() failed!!, ErrorCode = 0x%x\n",Err);
printf("Uart Interface Initialised\n");
logo();
Uart_Printf("\r\n\nCMD> ");
while(1)
{
if (Uart_GetString(command))
{
if (command[0] == 't' || command[0] == 'T')
{
// input link : 0~2
int cmd, link;
sscanf(command, "%c %d", &cmd, &link);
test_lte_cpri((CSL_Aif2LinkIndex)link);
}
else if (command[0] == 'a' || command[0] == 'A')
{
}
else
{
SelRW = decCmd(command, &addr, data, &NumData);
switch (SelRW)
{
case 'W':
Uart_Printf ("[WRITE %d BYTE DATA from 0x%08x]\r\n", NumData, addr_offset + addr);
for (i=0; i<NumData; i++) {
*(volatile int *)(addr_offset + addr+4*i) = data[i];
tmp = *(volatile int *)(addr_offset + addr+4*i);
Uart_Printf (" MEM[%08x] = %08x (%08x)\r\n", addr_offset + addr+4*i, data[i], tmp);
}
Uart_Printf ("\r\n");
break;
case 'R':
Uart_Printf ("[READ %d BYTE DATA from 0x%08x]\r\n", NumData, addr_offset + addr);
for (i=0; i<NumData; i++) {
tmp = *(volatile int *)(addr_offset + addr+4*i);
Uart_Printf (" MEM[%08x] = %08x\r\n", addr_offset + addr+4*i, tmp);
}
Uart_Printf ("\r\n");
break;
case 'O':
if (NumData > 0) {
addr_offset = (int)data[0];
}
Uart_Printf (" * ADDRESS OFFSET : 0x%08X\r\n", addr_offset);
Uart_Printf ("\r\n");
break;
default:
if (command[0] != 0)
{
Uart_Printf(" Bad Command !!!!\r\n");
Uart_Printf(" Command Format : Write Addr D1 D2 D3 ... DN\r\n");
Uart_Printf(" Read (Addr) (NumOfData)\r\n\r\n");
}
break;
}
}
Uart_Printf("CMD> ");
}
}
}
//////////////////////////////////////////////////////////////////////////////////////////////////////
//====================================================================
char Uart_IsKey(void)
{
/* Wait until FIFO is ready */
if( CSL_FEXT(hUart->LSR, UART_LSR_DR) == CSL_UART_LSR_DR_NOTREADY )
{
/* Delay processor for 20us */
BSLC667X_MicrosecWait(20);
}
else
{
return 1;
}
return 0;
}
//====================================================================
char Uart_GetKey(void)
{
return (Int8)hUart->RBR;
}
int Uart_GetString(char *string)
{
static int idx=0;
char *string2 = string;
char c;
if (Uart_IsKey())
{
c = Uart_GetKey();
if (c != '\r')
{
if(c=='\b')
{
if( (int)string2 < (int)(string+idx) )
{
Uart_Printf("\b \b");
idx--;
}
}
else
{
*(string + idx++) = c;
Uart_Printf("%c", c);
}
}
else
{
*(string+idx)='\0';
Uart_Printf("\r\n");
idx = 0;
return 1;
}
}
return 0;
}
int Uart_Printf (const char *fmt, ...)
{
va_list argptr;
char txbuf[512];
int cnt;
va_start(argptr, fmt);
cnt = vsprintf(txbuf, fmt, argptr);
va_end(argptr);
BSLC667X_UartPrint(txbuf);
return(cnt);
}
char decCmd (char *s, int *addr, unsigned int *data, int *NumData)
{
int i=0, ptr=0;
char s_cmd[128];
char cmd[32];
unsigned int data_cmd;
int addr_cmd, NumData_cmd;
if (sscanf (s, "%s", cmd) == EOF) return '\0';
while (s[i] == 0x20) i++; while ((s[i] != 0x20) && (s[i] != '\0')) i++;
strcpy(s_cmd, s+i);
if ((cmd[0]=='w') || (cmd[0]=='W')) {
if (sscanf ( s_cmd, "%x", &addr_cmd) == EOF) return '\0';
while (s[i] == 0x20) i++; while ((s[i] != 0x20) && (s[i] != '\0')) i++;
strcpy(s_cmd, s+i);
*addr = (addr_cmd);
while (sscanf (s_cmd, "%x", &data_cmd) != EOF) {
data[ptr++] = data_cmd;
while (s[i] == 0x20) i++; while ((s[i] != 0x20) && (s[i] != '\0')) i++;
strcpy(s_cmd, s+i);
}
data[ptr] = '\0';
if (!ptr) return '\0';
*NumData = ptr;
return 'W';
}
else if ((cmd[0]=='r') || (cmd[0]=='R')) {
NumData_cmd = 1;
if (sscanf(s_cmd, "%x", &addr_cmd) == EOF) {
*NumData = (int) NumData_cmd;
return 'R';
}
while (s[i] == 0x20) i++; while ((s[i] != 0x20) && (s[i] != '\0')) i++;
strcpy(s_cmd, s+i);
*addr = (addr_cmd);
sscanf (s_cmd, "%d", &NumData_cmd);
while (s[i] == 0x20) i++; while ((s[i] != 0x20) && (s[i] != '\0')) i++;
strcpy(s_cmd, s+i);
if (sscanf(s_cmd, "%d", &ptr) != EOF) return '\0';
*NumData = (int) NumData_cmd;
return 'R';
}
else if ((cmd[0]=='o') || (cmd[0]=='O')) {
if (sscanf (s_cmd, "%x", &data_cmd) != EOF) {
*NumData = 1;
data[0] = data_cmd;
}
else {
*NumData = 0;
}
return 'O';
}
else {
return '\0';
}
}
void logo (void)
{
Uart_Printf("\r\n");
Uart_Printf("\r\n");
Uart_Printf(" :::::::: ::::::::: ::::::::: ::::::::::: \r\n");
Uart_Printf(" :+: :+: :+: :+: :+: :+: :+: \r\n");
Uart_Printf(" +:+ +:+ +:+ +:+ +:+ +:+ \r\n");
Uart_Printf(" +#+ +#++:++#+ +#++:++#: +#+ \r\n");
Uart_Printf(" +#+ +#+ +#+ +#+ +#+ \r\n");
Uart_Printf(" #+# #+# #+# #+# #+# #+# \r\n");
Uart_Printf(" ######## ### ### ### ########### \r\n\r\n");
Uart_Printf("[ AMC-2C66-3AIF CONSOLE PROGRAM %s ]\r\n", __VERSION__);
Uart_Printf("[ Coded by CleverLogic Co.,Ltd. ]\r\n");
}
Vendor specific CPRI I send data I want to be.
I do not know what to do with the code.
Thanks,
gyosun
