• State Resolved
  • Locked Locked
  • Replies 18 replies
  • Subscribers 98 subscribers
  • Views 1729 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6678 pins state after the Power-on Reset

Daisuke Maeda
Guru 20215 points
Other Parts Discussed in Thread: PCA9306

Please tell me the C6678 pins state after the Power-on Reset.

"After the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until otherwise configured by their respective peripheral."

http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf
7.4.1 Power-on Reset (Page 125)

What are Z group pins, low group pins, high group pins?

Best regards,

Daisuke

 

  • 0
    TI__Mastermind 42545 points

    Table 2-15 breaks the IO signals into functional groups.  The type column defines the buffer type and the IPD/IPU column defines whether there is an internal pull up or pull down resistor.  IOZ and OZ buffers will be tri-stated once the PORz is released and the internal resistor, if present, will determine whether these pins are in a low state or a high state.  The pins are associated with internal peripherals and once the peripherals are enabled they may begin driving pins defined as outputs to a state that is different then value defined by the internal pulls.  You will need to check the users guide for the peripheral in question to determine the default state of the pins after the peripheral is enabled.

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for your reply.

    O buffers (e.g. MDCLK, SGMII0TXN, SGMII0TXP) can not be tri-stated.
    What state are these buffers once the PORz is released?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    All LVCMOS buffers in the C6678 with the exception of RESETSTATz are placed in high z when the part is in reset.  Some of these buffers become output only once the peripherial that uses them is removed from reset.  Let me address the specific instances from the data sheet.

    1) All serdes transmitters will be set to the appropriate common mode voltage when the serdes interface is disabled. 

    2) MDCLK is pulled high once the peripheral is released from reset.

    3) Hyperlink flow control outputs are in tristate until the hyperlink peripheral is released from reset.  Once it is released it will begin driving the flow control output signals and sending commands.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for your reply.

    I guess that the peripheral is removed from reset by PSC, that also the peripheral is in reset when the Power Domain State is OFF or the Module State is SwRstDisable.

    Are MDIO pins included in the Ethernet SGMIIs Clock Domain?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    Yes, the MDIO and MDCLK bits are part of the Ethernet subsystem.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for your reply.

    I found an information about the I/O Buffer Type.

    http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf
    6.4 Power Supply to Peripheral I/O Mapping (Page 111)

    What state are the output buffers except LVCMOS once the PORz is released?

    I guess the Open-drain buffers are placed in high z.
    Are other buffers placed in high z when the peripheral is in reset?

    Are all serdes transmitters set to the appropriate common mode voltage when the peripheral is in reset?

    Best regards,

    Daisuke

     

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Are MDIO and SGMII included in the Packet Coprocessor Power Domain?

    Is MDCLK pin placed in high z when the Power Domain State that include MDIO is ON and the Ethernet SGMIIs Module State is SwRstDisable?

    http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf
    Table 7-6 Power Domains (Page 120)
    Table 7-7 Clock Domains (Page 121)

    Best regards,

    Daisuke

     

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Are SGMII and MDIO included in the Most peripheral logic Power Domain?

    http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf
    Table 7-6 Power Domains (Page 120)

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    If you look at the Functional Block diagram figure 1-1 you will see a block labeled Network Coprocessor.  This block includes the Ethernet switch, the SGMIIs, the security accelerator and the packet accelerator.  In the list of power domains this is referred to as the Packet Coprocessor.  That is the reset that controls the MDIO and the SGMII.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for your reply.

    Which is the condition that MDIO's reset is released?

     a) Packet Coprocessor Block State is ON and Ethernet SGMIIs Module State is SwRstDisable

     b) Packet Coprocessor Block State is ON and Ethernet SGMIIs Module State is Enable

     c) Other condition

    Our customer designs a C6678 board.
    C6678 SGMII connect to SGMII of other device which is not PHY.
    Therefore, EMAC is enabled and MDIO interface is enabled.
    However, MDIO interface is not used.

    Best regards,

    Daisuke

     

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    When MDIO is in reset, is MDCLK pin pulled low by Internal-pulldown?

    http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf
    Table 2-15 Terminal Functions Signals and Control by Function (Page 48)

    While MDIO does not access PHY, are MDIO and MDCLK pins not driven?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    The MDIO block is controlled by the packet coprocessor reset.  It is not dependent on the state of the SGMII.  Once MDIO has been released from reset it will drive both the clock and data signals high.  If you're not connecting the MDIO interface to any other device simply leave the pins unconnected.  The outputs will not toggle unless you set the registers to send an access request.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for your reply.

    There are three Clock Domains included in NETCP, and they are LPSC7(Packet Accelerator) and LPSC8(Ethernet SGMIIs) and LPSC9(Security Accelerator).
    Is MDIO dependent on no Clock Domain Module State?

    http://www.ti.com/lit/ds/sprs691c/sprs691c.pdf
    Table 7-7 Clock Domains (Page 121)

    Best regards,

    Daisuke

     

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Is MDIO's reset dependent on only Packet Coprocessor Block Power Domain State?

    Best regards,

    Daisuke

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for answering my many questions.

    Our customer designs other C6678 board too.
    MDIO connect to PHY on the board.

    I want to confirm whether my understanding is correct.

    When the Packet Coprocessor Block of PSC is in OFF state,

     - MDIO pin: The output buffer is High-Z and the internal pull-up resistor is active.

     - MDCLK pin: The output buffer is High-Z and the internal pull-down resistor is active.

    When the Packet Coprocessor Block of PSC is in ON state and MDIO is in IDLE or turnaround,

     - MDIO pin: The output buffer drives it to VOH and the internal pull-up resistor is active.

     - MDCLK pin: The output buffer drives it to VOH and the internal pull-down resistor is active.

    Is my understanding correct?

    Best regards,

    Daisuke

     

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Our customer needs an answer immediately!

    I would appreciate if you respond within two days.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 42545 points

    Hi Daisuke,

    Your understanding is correct.  Note that the internal pull-up and pull-down resistors are only designed to keep an unused interface in a steady state and are not intended to be used as a pulling resistor if the signal is connected on the PCB.  You have stated in previous posts that you are not planning on using this interface.  If you are not using the interface and the balls are left unconnected, the internal pulling resistors are sufficient to keep the IOs in a steady state.  If you are connecting any trace to the ball on the PCB then you should include an external pulling resistor.  This is true for all pulling resistors on all the LVCMOS IOs for the part.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Guru 20215 points

    Hi Bill,

    Thank you for your reply.

    Our customer is going to design other board too which is equipped with PHY.

    I have the question about the MDIO internal resister.
    Does the MDCLK pin have an internal pull-up resistor not pull-down?

    C6678EVM was used for the confirmation of the MDIO signals.
    On the MDIO signal lines, the external pull-up resistor (R85, R957) was removed, and the voltage level translator (PCA9306) outputs are High-Z (EN = Low, VREF2 = Low). 
    Boot Mode Pins were set for No boot mode.
    Once EVM is powered up or released from reset (RST_FULL1 button) the MDCLK signal is high.

    Best regards,

    Daisuke