Hello all.
I'm working on a DM8148 based board and we're going to routing a DDR3 system on it. We'll use 4 DDR3 x16 device, two for each DDR bank.
My question is: I can't find a clarification about how many lenght matching costraint is needed between segments called AT in SPRS647d.
In table 8-73 at point NO.13 and 14, AT skew specification is different between address and clocks.
I think it means that CLK respect CLK# must be matched under 5mils length and ADDR_CTRL group must be matched under 100mils length.
I don't understand if CLK group has to be matched in respect of ADDR_CTRL group or if I can keep the length less then 500mils without any other costraint.
Thank in advance.
