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Verifying the Selection of C6747 for Medical Application

Other Parts Discussed in Thread: ADS1299

Hi

I have selected the C6747 DSp for a medical application. The main tasks are The DSp needs to receive via SPI and DMA samples from ADS1299. T

hese samples needs to be

1. Highpass filtered

2. Notch filtered

3 Artefact filter ed

then send the processed samples  over ethernet to a PC board running CE.

 

I need to know the:

overheads in the SPI DMA communications

the cycle count for the ethernet communications

the cycle count per tap for the various filtering functions

 

Last, the on-chip memory size is rather small. Can such memory size fit the code for the above tasks?

Regards

 

  • Hatem,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    On TI.com, you can look for Applications where there are examples for many different products. There does not appear to be anything specific to Medical Applications in your list.

    Why have you selected the C6747 for this product? Have you considered the C6748 (DDR3 support) or C6655 (upgradable to dual-core C6657)? If not, I recommend you do consider these devices as newer technology, especially the C6654/55/57 if you have concerns about system throughput.

    With your EVM or experimenter Kit for any of these devices, you will be able to try out examples that use SPI and Ethernet to help you determine overhead numbers that match what you mean to be asking about. With that board or the simulator, you will be able to code up your filters and take measurements to determine the cycle count requirements.

    Hatem Yassine said:
    the on-chip memory size is rather small. Can such memory size fit the code for the above tasks?

    There is not enough information to determine this. And the cache features make it very easy to keep many parts of your code in the external memory and still get good speed performance during the execution. As above, your testing of the system on an EVM will prove this out for you.

    Regards,
    RandyP

  • Thanks RandyP.

     

    I can see little difference between the C6747 & C6748. Do you notice a big difference?

     

    For the C6655 Yes, but It is expensive.  I have noticed there is 1 MB of Cache. I assume this can all be used as program/data memory.  Is this possible on the C6655?

    I agree about the comment regarding the memory size.  What I really should have said.

    Is it normal for this DSP (C6747) to be used where the code and data resides in external memory?

    What is the penalty in cycle count between residing the code in the internal memory vs external memory?

     

     

     

  • Hatem,

    The biggest difference is the external memory interface. The C6747 uses 133MHz SDRAM and the C6748 uses 150MHz DDR2. I assume it would save money if you can use the C6748 with one 16-bit DDR2 device and get the same or better performance (I have not benchmarked this, but it seems right) than the C6747 with two 16-bit SDRAM devices. Your application's performance could see a lot more benefit from that DDR2, or it could lose some of the benefit - it depends on how the memory is used.

    It looks like the C6748 is a little lower cost for the 456MHz part.

    The C6655 does cost about three times as much for more than 2x the clock speed and a whole lot more external memory bandwidth, so it will be worth it if you need the performance. The C6654 is a bit more cost-effective, again depending on what performance you need.

    It is "normal" for every one of our DSPs to be used where the code and data resides in external memory. Some applications require some of the program or some of the data to be kept in internal SRAM, so the flexible cache/RAM allocation allows you to make the tradeoff that fits your application the best. The most common case I see is maximizing L1P and L1D cache. Then half the time L2 cache is maximized and half the time L2 is all SRAM.

    The cache gives a big performance increase to the effective use of the external memory. DSP algorithms are usually (or can be) memory-linear meaning they move through a section of memory rather than randomly accessing all over the place.

    Hatem Yassine said:
    What is the penalty in cycle count between residing the code in the internal memory vs external memory?

    This is totally application-dependent. You would write up a portion of your program and test it in the different memory configurations and measure the differences.

    Regards,
    RandyP