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L1 Cache on TMS320C6713

Tom Clary
Prodigy 100 points
Other Parts Discussed in Thread: TMS320C6727

There is an abundance of information on cache usage for the C6000 family. I'm wading through it as fast as I can but I have not been able to determine a few simple things. I am trying to benchmark some of our algorithms on a TMS320C6713. I am running from L2 Memory. Our full application would easily fit here so off chip memory is not a concern. I have a few questions. 

1) How can I either tell if the L1 caches are enabled or more specifically enable them. I've found routines in various support libraries to invalidate them. But nothing that seems directed to enabling them.

2) Since I am running out of L2 memory, does enabling L2 cache help any? From an architecture picture, there does seem to a different data path to the L1 program cache. So that might help.

It looks like I will get to do this all again when I move on to evaluate the TMS320C6727 as it looks to have a different cache architecture.

  • 0
    Prodigy 100 points

    This seems to sort of answer 1. From SPRU401J B.1.18

    The cache enable (CE) bit in each MAR determines whether the L1D, L1P, and L2 are allowed to cache the corresponding address range. After reset, the CE bit in each MAR is cleared to 0, thereby disabling caching of external memory by default. This is in contrast to L2 SRAM, which is always considered cacheable.

  • 0
    TI__Guru*** 125430 points

    Tom Clary said:
    1) How can I either tell if the L1 caches are enabled or more specifically enable them. I've found routines in various support libraries to invalidate them. But nothing that seems directed to enabling them.

    Make sure you read this one:

    TMS320C621x/C671x DSP Two-Level Internal Memory Reference Guide
    http://www.ti.com/lit/spru609

    See Section 7.1 "Cache Mode Selection" in the above document.  In summary, L1P and L1D are enabled by default on reset and there's no other way to configure L1P/L1D for this particular family.

    Tom Clary said:
    2) Since I am running out of L2 memory, does enabling L2 cache help any? From an architecture picture, there does seem to a different data path to the L1 program cache. So that might help.

    L2 cache only helps you if you have program/data in external memory.  If you can turn the L2 cache entirely off (which will give you more space as SRAM) and fit all your code/data in L2 then that will be the best performance.  Otherwise you'll have to do some system level testing/analysis to determine the best tradeoff of cache vs SRAM and which code/data should be put in external memory.

  • 0 in reply to Brad Griffis
    Prodigy 100 points

    Brad, thanks for your reply. I had glanced at the referenced document but had not looked at it in depth. I believe things have been answered sufficiently for the 'C6713 for what I am immediately evaluating. Is there an equivalent to SPRU609 for the 'C6727?

    I do have a follow on question that is mainly of future interest. Caches always introduce the issue of what regions of memory can be validly be cached. The L2 cache has mechanisms to define this for certain external memory regions. I haven't seen where the L1D has similar mechanism. It is a write through so writes seem to be covered. How does the L1D account for either DMA updates to L2 or other regions memory mapped devices?

  • 0 in reply to Tom Clary
    TI__Guru*** 125430 points

    Tom Clary said:
    Brad, thanks for your reply. I had glanced at the referenced document but had not looked at it in depth. I believe things have been answered sufficiently for the 'C6713 for what I am immediately evaluating. Is there an equivalent to SPRU609 for the 'C6727?

    The c6727 has only L1P, i.e. there is NOT any L1D or L2 memory.  There's not a "two level memory guide" since there is only one level of memory!  (Much simpler...)

     

    Tom Clary said:
    Caches always introduce the issue of what regions of memory can be validly be cached. The L2 cache has mechanisms to define this for certain external memory regions. I haven't seen where the L1D has similar mechanism. It is a write through so writes seem to be covered. How does the L1D account for either DMA updates to L2 or other regions memory mapped devices?

    No, none of the c6000 devices use a write through cache.  All of our caches are "write back" caches.  Please review the definitions in Section 2 of the Two Level Internal Memory Reference Guide.  Along those lines please also see the definition of "snoop" as that is the means by which coherence is maintained for the L2 SRAM.  Read Section 8.2 "EDMA Coherence in L2 SRAM Example" and perhaps have a printout of the terminology (Chapter 2) as you're doing so.  A lot of the difficulty in cache is simply knowing the terms.