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DM3730 Power Integrity requirments

Dear All,

TI has publish an application notes where it is clearly explained the VDD_MPU_IVA / VDD1 power requirments (AC and DC). http://www.ti.com/litv/pdf/sprabj7

They are very clear about the fact that the maximun IR drop on the net/plane from PMIC to DM37xx should not be more that 12mV (if sense is not used). On the beagle boardXM this power net has been routed with a long net (not plane) and the extimated voltage drop it is more than 100mV @ 1.4A. For having a drop around 15mV the current shouldn't be bigger than 200mA.

Any advice?

Kind Regards,

OSCAR M.

  • Hi Oscar,
     
    The Beagleboard XM is definitely not the best example. When designing your own board my advice is that you follow the application note SPRABJ7.PDF guidelines. Use large planes on the large current supplies.
  • Hi Biser,

    thank you for your reply. Very Illuminating and worring at the same time.

    The SPRABJ7.PDF has been released years after the chip and it talks about only the VDD_MPU_IVA voltage. The problem is that we have already developed many boards using the beagle-board as reference design, and we still not have any info, regarding power requirements (AC and DC) for all the other power supply.

    In your opinion, do you recommend to re-design our products (they work perfectly) and could you suggest where we could get the missing info. (ex. Z target for each power net)

    Kind Regards,

    OSCAR M. 

  • Hi Oscar,
     
    I would definitely not recommend to you redesigning any product that works perfectly, as you say. However for new products you should pay attention on the VDD_MPU_IVA and VDD_CORE supplies. There are no particular  requirements on VDD_CORE, except for proper and adequate decoupling. For VDD_MPU_IVA I can give you some figures that are used for OMAP3 analisys, which should apply for DM37X too:
     
    Processor: OMAP3 @ 1GHz
    VDD_MPU_IVA: 1.2V @ 1.25A
    Recommended decoupling capacitors: 2x22uF + 8x100nF + 2x47nF + 2x10nF
    Maximum voltage drop at OMAP balls: 2.5% (30mV) or 0.5 - 1% (6 - 12mV) if VRM sense line/point is distant from OMAP
    DC resistance from PMIC to OMAP, GND included: 24mOhm or 5 - 10mOhm  if VRM sense line/point is distant from OMAP
    Loop inductance: <1.5nH per decoupling capacitor (capacitor ESL included) or <1.0nH per decoupling capacitor (capacitor ESL excluded)
    Z target: 96.4mOhm @ 50MHz