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TI814x EVM SDRAM Config - Row Size Question

eric cina
Prodigy 70 points

Hi,

I'm looking at the ddr_defs_ti814x.h for U-Boot in the EZSDK 5.05.01.04.  I see the following macro being used to set the SDRCR (SDRAM config) register:

#define DDR3_EMIF_SDRAM_CONFIG 0x61C011B2

This would seem to set the number of Row Bits to 12 but the DDR3 memory on the board specifies 14 Row Bits.  Also there are 14 address bits wired to the memory.  Am I missing something here?  Can somebody clarify this for me? 

Thanks,

Eric

  • 0
    TI__Guru**** 393215 points
    Hi Eric,
     
    Please check the note on top of the ROWSIZE description in DM814X TRM Table 7-37: Row Size Selection. Don't care if both EBANK_POS and IBANK_POS are 0. In your case IBANK_POS is 0, and I'm pretty sure that EBANK_POS (which is in DDR3_EMIF_SDRAM_CONFIG2) is also 0.