DDR SRIO Reference Clock issue

Please explain more about what you want to do, and please use signal names from the data manual so we will know exactly what you are talking about.

The DDR3 clocking is very flexible, with its own input clock plus a programmable PLL. I do not understand why you expect a 66MHz requirement, so please explain why you expect this.

200MHz is a very high frequency to have on a device input pad, but it is within the PLL spec. Please see the Data Manual for the range of values allowed for the PLL input (DDRCLKN/P) and for the range of values allowed for the DDR3 output clock (DDRCLKOUTN0/N1/P0/P1).

The SRIO clock and PLL choices are also listed in the Data Manual and in the SRIO User Guide. If there are some points in either document that are unclear, please refer to those places and let us know your question.

A very good choice is to use the components and settings as are implemented on the EVM. You will need to apply engineering analysis even to a copy of the EVM for your board design, of course.

Regards,
RandyP

There are a couple of questions raised by your post.  First the DDRCLKP/N frequency range is 40MHZ to 312.5MHz which is used as an input into the DDR PLL.  That PPL can be used to generate a broad range of clocks for the DDR subsystem.  For example the 66.67MHz clock provided on the EVM can be multiplies by 20 and then divided by 2 to get a 666.67MHz clock for DDR3-1333 memory devices or it can be multiplied by 12 and then divided by 2 to get 400MHz for DDR3-800 memory devices.  The output of the DDR PLL should always equal the clock rate for your DDR3 memory interface.

The second issue concerns the SRIOSGMIICLKP/N input.  The serdes reference clocks are limited to specific reference frequencies and must meet the jitter mask published in the Keystone I hardware design guide.  The only acceptable reference clock frequencies for SRIO are 156.25MHz, 250MHz or 312.5MHz.

Regards, Bill