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can processor stalling be prevented?

Jay Buhr
Prodigy 90 points

i am running a "bare metal" DSP application from shared memory (program text and data are linked around $8001000).  I have been timing portions of my sw using the internal timer TSCL.

when i inspect the assembler listings, i see that a small number of instructions can take inordinately long to execute -- the code snippet below was measured to take 144 processor cycles.  Processor interrupts are disabled.  There is no DMA, etc going on.

     379 00000158 022803e2             MVC     .S2     TSCL,B4           ; |255|

     380 0000015c 03800d6e!            LDW     .D2T2   *+DP(_az_phase_accumulator+4),B7 ; |256|

     381 00000160 02800b6e!            LDW     .D2T2   *+DP(_az_ref_accumulator+4),B5 ; |256|

     382 00000164 04000c6e!            LDW     .D2T2   *+DP(_az_phase_accumulator),B8 ; |256|

     383 00000168 03000a6e!            LDW     .D2T2   *+DP(_az_ref_accumulator),B6 ; |256|

     384 0000016c     9dc5             STW     .D2T2   B4,*+SP(48)       ; |255|

     385 0000016e     4c6e             NOP             3

     387 00000174     eadb             SUB     .S2     B7,B5,B5          ; |256|

     388 00000170 031905fb  ||         SUBU    .L2     B8,B6,B7:B6       ; |256|

     389                   

     390 00000178 022803e2             MVC     .S2     TSCL,B4           ; |258|

i am thinking that memory caching is to blame, and that the processor is stalling while the cache is filled -- however i have disabled the L2 cache and frozen the L1 program and data caches.

is there any way to completely prevent the caching h/w from running?  Or am i competely mistaken about the cache, and is something else to blame for stalling?

  • 0
    Guru 31670 points

    I am not an expert in DSP architecture. But if you are suspecting the cache fill as the reason for CPU stall, you can try increase/reduce the cache line size if its configurable in DSP. This will have a linear effect on the stall duration, if cache fill is the cause of stall.

  • 0 in reply to Renjith Thomas
    Prodigy 90 points

    i tried reducing the cache size to 0 in L1PCFG, on the assumption that if the processor had no place to put cached memory, it would have no reason to cache it.  This didn't help.

    my main problem is the non-determinism of the cache -- i have an interrupt handler which is executing every 100 microseconds, and if the processor goes AOL for 10 microseconds or so, it is a disaster.

    Since the memory i am using is all on-chip, wait states are not an issue, so the caching hw doesn't buy me anything.

  • 0 in reply to Jay Buhr
    Guru 31670 points

    Jay,

    Where are these LDW, STW reading and writing from/to? Is it an external memory or all on-chip?

  • 0 in reply to Renjith Thomas
    Prodigy 90 points

    they are all on-chip -- that is the annoying thing -- program data and text are both mapped into shared memory.