Hello,
In DM648 EVM board, there is a PLL ic to support 2 clock signal (SYSCLK & DDRCLK) into DM648 chip.
But we cancelled it in our new board, and used an OSC chip(27Mhz) and 2 buffers (one feed into SYSCLK, another DDRCLK).
Is it a good idea? or it will cause some problems when JTAG loadding program? (Timing unstable?)
Thanks!
Marc
