• State Resolved
  • Locked Locked
  • Replies 15 replies
  • Subscribers 99 subscribers
  • Views 873 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

chip select 1 for 8168

Mohamed Asif
Intellectual 580 points

Hello All

How to enable chip select 1 in 8168. 

Chip select 0 we are using for NAND.

Regards

Asif

  • 0
    TI__Guru**** 170625 points

    Hi Asif,

    The GPMC_CS1n is enabled through setting bit GPMC_CONFIG7_1[6] CSVALID = 0x1 (CSn enabled).

    Best Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 580 points

    Hi Pavel

    I am not able to set this bit from u-boot level.

    by default the bit is high   cs0 and cs1

    I am doing the following step

     The Base address 0x50000000

    UBOOT # md.w 0x50000060 0x10
    50000060: 0800 0000 0500 0007 0500 0007 0601 0601    ................
    50000070: 0705 0104 0480 1f0f   0048  0000 FF00  FFFF   ........H.....

    UBOOT # mw.w 0x50000060 0x0000 0x01

    UBOOT # mw.w 0x50000062 0x0000 0x01
    UBOOT # mw.w 0x50000064 0x0000 0x01

    UBOOT # mw.w 0x50000066 0x0000 0x01
    UBOOT # mw.w 0x50000068 0x0000 0x01

    UBOOT # mw.w 0x5000006a 0x0000 0x01
    UBOOT # mw.w 0x5000006c 0x0000 0x01

    I try ed  to set bit low and high but in both the case I am not able to see any out put. All ways the bit is high (checking in CRO)

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    TI__Guru**** 170625 points

    Hi Asif,

    There are several requirements, before enable the chip-select. Check DM816x TRM:

    section 9.2.4.8.1 Chip-Select Base Address and Region Size

    section 9.3.4 GPMC Configuration in NAND Mode - here the very last step is enable chip-select (when all parameters are configured)

    I hope this will help.

    Regards,

    Pavel




  • 0 in reply to Pavel Botev
    Intellectual 580 points

    Hi Pavel

    As per TRM Document for CHIP SELECT 1 (cs1)  GPMC_CONFIG7_i  bit 6 we have send for zero.

    but when i am try to send  GPMC_CONFIG7_i[6]  to zero it is hanging. I try from driver level, and also from u-boot level.

    your input will help us.

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    Intellectual 580 points

    sorry there is some spelling mis take

    Hi Pavel

    As per TRM Document for CHIP SELECT 1 (cs1)  GPMC_CONFIG7_i  bit 6 we have set for zero.

    but when i am try to set  GPMC_CONFIG7_i[6]  to zero it is hanging. I try from driver level, and also from u-boot level.

    your input will help us.

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    TI__Guru**** 170625 points

    Hi Asif,

    What kind of peripheral is attached to the GPMC_CS1n pin?

    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 580 points

    Hi Pavel

    The peripheral device is xr16l788 it is octal uart.

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    TI__Guru**** 170625 points

    Asif,

    Which address you are using to access the GPMC_CONFIG7_1 register? Can you try with 0x500000A8?

    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 580 points

    Hi Pavel

    I try with that  address 0x5000000a8 but it is not working.

    Also I try ed in following way.

    Removing NAND chip select 0 and connecting  chip select 1 to nand  and in u-boot code changing 0x60 to 0x90.  I am able to see chip select 1 signal in CRO.

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    TI__Guru**** 170625 points

    Hi Asif,

    By default GPMC_CONFIG7_0[6] CSVALID (CS0) is 0x1 and GPMC_CONFIG7_1[6] CSVALID (CS1) is 0x0.

    I successfully set GPMC_CONFIG7_1[6] CSVALID (CS1) to 0x1 in u-boot.

    First I print the value of GPMC_CONFIG7_1 register in address 0x500000A8 like this:

    TI8168_EVM#md.l 0x50000000
    50000000: 00000060 00000000 00000000 00000000    `...............
    50000010: 00000008 00000001 00000000 00000200    ................
    50000020: 00000000 00000000 00000000 00000000    ................
    50000030: 00000000 00000000 00000000 00000000    ................
    50000040: 00001ff0 00000000 00000000 00000000    ................
    50000050: 00000012 00000101 00000000 00000000    ................
    50000060: 00001810 001e1e00 001e1e00 16051807    ................
    50000070: 00151e1e 16000f80 00000048 0000ffff    ........H.......
    50000080: 00000000 00000000 00000000 00000000    ................
    50000090: 00001000 00101001 22060514 10057016    ...........".p..
    500000a0: 010f1111 8f070000 00000f00

    The value is the one marked in red colour, 0x00000f00, which means that by default the CS1 is 0x0, base address is 0x0 and CS size is 16MB. Then I enable CS1 like this:

    TI8168_EVM#mw.l 0x500000A8 0x0F40
    TI8168_EVM#md.l 0x50000000
    50000000: 00000060 00000000 00000000 00000000    `...............
    50000010: 00000008 00000001 00000000 00000200    ................
    50000020: 00000000 00000000 00000000 00000000    ................
    50000030: 00000000 00000000 00000000 00000000    ................
    50000040: 00001ff0 00000000 00000000 00000000    ................
    50000050: 00000012 00000101 00000000 00000000    ................
    50000060: 00001810 001e1e00 001e1e00 16051807    ................
    50000070: 00151e1e 16000f80 00000048 0000ffff    ........H.......
    50000080: 00000000 00000000 00000000 00000000    ................
    50000090: 00001000 00101001 22060514 10057016    ...........".p..
    500000a0: 010f1111 8f070000 00000f40 00000000    ........@.......
    500000b0: 00000000 00000000 00000000 00000000    ................
    500000c0: 00001000 00101001 22060514 10057016    ...........".p..
    500000d0: 010f1111 8f070000 00000f00

    Now the value of 0x500000A8 is 0x00000f40, which means that CS1 is enabled.

    Are you using the latest EZSDK 5.05.01.04 with u-boot-2010.06-psp04.04.00.01?


    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 580 points

    Hi pavel

    Thanks for your input. I am able to see the chip select 1 on CRO

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    TI__Guru**** 170625 points

    Hi Asif,

    I am glad you find a solution.

    Can you share what exactly resolved the issue?

    Thanks.

    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 580 points

    Hi Pavel

    By Default chip select 0 to 5 are pull up.

    For cs0 we have connected nand flash, For cs1 we have connected with xr16l788 ic 

    When boot up CS0 will go low because we are read the data. This will conform that CS0 is fine.

    To conform CS1 is working or not we had a some issues it may be hardware or software.

    With the following command it conform that CS1 is fine.

    Also from the driver level it is working fine.

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    Intellectual 580 points

    Hello All

    From driver level code

            gpmc_cs_write_reg(cs1,0x18,0x00);
            msleep(2000);

            printk("after sleep 1\n");

            l = GPMC_CONFIG1 + (0x30 * cs1);
            gpmc_write_reg(l,0x00000800);

            l = GPMC_CONFIG2 + (0x30 * cs1);
            gpmc_write_reg(l,0x00070500);

            l = GPMC_CONFIG3 + (0x30 * cs1);
            gpmc_write_reg(l,0x00070500);

            l = GPMC_CONFIG4 + (0x30 * cs1);
            gpmc_write_reg(l,0x06010601);

            l = GPMC_CONFIG5 + (0x30 * cs1);
            gpmc_write_reg(l,0x01040705);

            l = GPMC_CONFIG6 + (0x30 * cs1);
            gpmc_write_reg(l,0x1F0F0480);

            l = GPMC_CONFIG7 + (0x30 * cs1);  //chip select size 16MB, cs enabled
            gpmc_write_reg(l,0x00000F40); //asif F44);
            msleep(2000);

            printk("after sleep 2\n");

    Once it is done you have to read the data to see the CS1 signal in CRO.

    Regards

    Asif

  • 0 in reply to Mohamed Asif
    Intellectual 420 points

    Hi All,

    I have a similar problem to what's above.  The problem i'm having is that we have nothing connected to Chip Select 0 or 1 but we have our NAND connected to Chip Selecte 2.   

    I know we can't boot from it but i would like to try and test the nand after bootup.  I have not been able to make that change, does anyone know how to do this?  

    Thanks!

    Rodrigo