Hi,
I'm trying to use the AM3359 with SPI1 as slave only (clk in, Data in and CS pins).
I 'm confronting with the problem of synchronisation.
I test with a master device which send continuously a WL 16 bits data. Betwen each 16 bits words, the CS passed in the state of inactive.
For example, with WL with 16 bits, when i activated the channel (CH0CTRL = 0x01), there are 2 cases :
1- Master device hasn't tranfert any word yet, and begin to send this 16 bits after the activation of the channel :
-> Everything work find
2-Master device has tranfert some bit before the activation of the channel,
-> Every words in RX buffer is shift. AM3359 doesn't reset the shift register when CS is inactive.
How can i reset this shift register when CS passed in inactive mode ?
Here is my configuration :
//soft reset
iowrite32(0x00000002, McSPI_virt_addr + McSPI_SYSCONFIG);
//check reset is done
do{
retval = ioread32 (McSPI_virt_addr + McSPI_SYSSTATUS);
}while (retval!=0x01);
//slave mode + testmode
iowrite32(0x0000000C, McSPI_virt_addr + McSPI_MODULCTRL);
//set pin inout
iowrite32(0x00000600, McSPI_virt_addr + McSPI_SYST );
//Rx mode / RX on D1 / 16bits / Mode 0 / RX FIFO / NO DMA
iowrite32(0x100617C0, McSPI_virt_addr + McSPI_CH0CONF);
//McSPI_XFERLEVEL AEL & AFL => 16octets
iowrite32(0x00000F0F, McSPI_virt_addr + McSPI_XFERLEVEL );
//slave mode
iowrite32(0x00000004, McSPI_virt_addr + McSPI_MODULCTRL);
//activate CH0
iowrite32(0x00000001, McSPI_virt_addr + McSPI_CH0CTRL);
