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I am using c6748.
EDMA ping pong transfer is setup to transfer data from the codec with MCBSP0 .
When I do not use the EDMA and receive data from the codec via the MCbSP0, data seems fine.
But, when enable EDMA and view the recived data, it looks corrupted almost like rubbish...
Any idea what sort of discrepancy would occur between the McBSP0 and EDMA
regards
izzet
Hi,
In which software ( Example: Linux, Starterware), you are trying this?
whether the code is sample code or customized one?
Please provide your McBSP, EDMA configuration details and debug information.
-Regards,
Balaji N
Hi
I am using CSL on C6748 nothing else..
get codec data via McBSP0 to the DSP via EDMA3CC0.
Below is the code that I use to do configuration of the EDMA3.
I do not know if it is true or not if I use the following codes after setting up event PARAMs, my code seems to be working fine.
regIPR = edma3ccRegs->IPR;
edma3ccRegs->ICR |= 0x00000004;
if I delete them it is not always correct. Interupts are messed up or something. data is corrupted.
I know that I need to clear any pending interrupts. But the question no other edma transfer is setup or occuring.
so why do i need to clear IPR while there should be nothing....
of course this could a coincedence ...
best regards
#include "edma.h" //#include "mcasp.h" #include "SignalProcessing.h"
#define EDMA_EVENT0 (Uint8)0u #define EDMA_EVENT1 (Uint8)1u
#define EDMA_EVENT2 (Uint8)2u //#define EDMA_EVENT0 (Uint8)0u #define EDMA_EVENT3 (Uint8)3u //#define EDMA_EVENT1 (Uint8)1u
#define EDMA_PARAMETER_SET0 (Uint8)0 #define EDMA_PARAMETER_SET1 (Uint8)1
#define EDMA_PARAMETER_SET32 (Uint8)(32) #define EDMA_PARAMETER_SET33 (Uint8)(33)
#define EDMA_PARAMETER_SET34 (Uint8)(34) #define EDMA_PARAMETER_SET35 (Uint8)(35)
extern CSL_McbspRegsOvly mcbsp0Regs;
/* 16.2.3.2.3 Channel Destination Address(DST) The32-bit destination address parameter specifies the starting byte address of the destination.For DAM in increment mode,there are no alignment restrictions imposed by EDMA3.For DAM in constant addressing mode,you must program the destination address to be aligned to a 256-bit aligned address (5 LSBsofaddressmustbe0).TheEDMA3TC will signal an error, if this rule is violated. See Section16.2.11.2for additional details. */ #pragma DATA_SECTION (pingRcvBuffer_L, ".EdmaData") Int32 pingRcvBuffer_L[NUM_OF_SAMPLES_PER_BUFFER]; #pragma DATA_SECTION (pingRcvBuffer_R, ".EdmaData") Int32 pingRcvBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pongRcvBuffer_L, ".EdmaData") Int32 pongRcvBuffer_L[NUM_OF_SAMPLES_PER_BUFFER]; #pragma DATA_SECTION (pongRcvBuffer_R, ".EdmaData") Int32 pongRcvBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pingXmtBuffer_L, ".EdmaData") Int32 pingXmtBuffer_L[NUM_OF_SAMPLES_PER_BUFFER]; #pragma DATA_SECTION (pingXmtBuffer_R, ".EdmaData") Int32 pingXmtBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pongXmtBuffer_L, ".EdmaData") Int32 pongXmtBuffer_L[NUM_OF_SAMPLES_PER_BUFFER]; #pragma DATA_SECTION (pongXmtBuffer_R, ".EdmaData") Int32 pongXmtBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
Int32 *pingDataPointer, *pongDataPointer; Uint32 regIPR; /*#pragma DATA_SECTION(RcvBuffers,"mysection") #pragma DATA_SECTION(XmtBuffers,"mysection")*/
//Int32 TestData[NUM_OF_SAMPLES_PER_BUFFER*8];
/*
#pragma DATA_ALIGN(pingRcvBuffer_L, 128); #pragma DATA_ALIGN(pingRcvBuffer_R, 128); #pragma DATA_ALIGN(pongRcvBuffer_L, 128); #pragma DATA_ALIGN(pongRcvBuffer_R, 128);
#pragma DATA_ALIGN(pingXmtBuffer_L, 128); #pragma DATA_ALIGN(pingXmtBuffer_R, 128); #pragma DATA_ALIGN(pongXmtBuffer_L, 128); #pragma DATA_ALIGN(pongXmtBuffer_R, 128); */
/* #pragma DATA_ALIGN(TestData, 256); */ /*Int32 tone[60] ={ 32768, 32588, 32052, 31164, 29935, 28378, 26510, 24351, 21926, 19261, 16384, 13328, 10126, 6813, 3425, 0, -3425, -6813, -10126, -13328, -16384, -19261, -21926, -24351, -26510, -28378, -29935, -31164, -32052, -32588, -32768, -32588, -32052, -31164, -29935, -28378, -26510, -24351, -21926, -19261, -16384, -13328, -10126, -6813, -3425, 0, 3425, 6813, 10126, 13328, 16384, 19261, 21926, 24351, 26510, 28378, 29935, 31164, 32052, 32588}; Uint32 tone_pointer = 0;
Int32 TmpBuffer[NUM_OF_SAMPLES_PER_BUFFER]; #pragma DATA_ALIGN(TmpBuffer,8);*/
Uint16 PingPongFlag_Rcv = 1; Uint16 PingPongFlag_Xmt = 1; Uint16 i;
Uint8 IntTriggered =1; extern Int16 interrupt_counter; extern Int16 run; extern Uint16 ModeChange;
Int32 *audio_out;
/*---------------------------------------------------------------------------*/
void SetupEDMA (void) { Uint16 i;
// Write EMCR, CCEERCLR, ECR registers to clear the EMR, CCERR, ER // EMCR = 0xFFFFFFFF; CCERRCLR = 0xFFFFFFFF; ECR = 0xFFFFFFFF; // EDMA event 0-- McASP0 Receiver // EDMA event 1-- McASP1 Transmitter // EDMA event 2-- McBSP0 Receiver // EDMA event 3-- McBSP1 Transmitter // Clear Event Registers CSL_FINST(edma3ccRegs->ECR, EDMA3CC_ECR_REG, MASK); CSL_FINST(edma3ccRegs->SECR, EDMA3CC_SECR_REG, MASK); //CSL_FINST(edma3ccRegs->IECR, EDMA3CC_IPR_REG, MASK); //CSL_FINST(edma3ccRegs->ICR, EDMA3CC_IPR_REG, MASK);
edma3ccRegs->ECR = 0xffffffff; // clear events 0 -> 31 edma3ccRegs->SECR = 0xffffffff; // clear secondary events 0 -> 31 edma3ccRegs->IECR = 0xffffffff; // disable all interrupts edma3ccRegs->ICR = 0xffffffff; // clear all pending interrupts
// Enable Channel 0 - 1 to DSP (Region 1 ) // CSL_FINST(edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE, EDMA3CC_DRAE_E2, ENABLE); // CSL_FINST(edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE, EDMA3CC_DRAE_E3, ENABLE); ///////////edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE = CSL_FMKT(EDMA3CC_DRAE_E0, ENABLE) | CSL_FMKT(EDMA3CC_DRAE_E1, ENABLE); edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE = CSL_FMKT(EDMA3CC_DRAE_E2, ENABLE) | CSL_FMKT(EDMA3CC_DRAE_E3, ENABLE);
// Assign Channel 0 - 1 to Queue 0 ///////////edma3ccRegs->DMAQNUM[1] = CSL_FMKT(EDMA3CC_DMAQNUM_E0, Q0) | CSL_FMKT(EDMA3CC_DMAQNUM_E1, Q0); edma3ccRegs->DMAQNUM[0] = CSL_FMKT(EDMA3CC_DMAQNUM_E2, Q0) | CSL_FMKT(EDMA3CC_DMAQNUM_E3, Q0);
// Initialize PaRAM Transfer Context for Events 0 - 1 init_PaRAM_McASP_Rcv_event0(); init_PaRAM_McASP_Tx_event1();
// Enable channel 0 and 1 ///////////CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E0, SET); CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E1, SET); CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E2, SET); CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E3, SET);
// Enable interrupt 0 and 1 CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I2, SET); ///////////CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I0, SET); //CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I3, SET);
//regIPR = edma3ccRegs->IPR; //edma3ccRegs->ICR |= 0x00000004;
// Initialize buffers
for(i = 0; i < NUM_OF_SAMPLES_PER_BUFFER; i++) { pingRcvBuffer_L[i] = 0; pingRcvBuffer_R[i] = 0; pongRcvBuffer_L[i] = 0; pongRcvBuffer_R[i] = 0; pingXmtBuffer_L[i] = 0; pingXmtBuffer_R[i] = 0; pongXmtBuffer_L[i] = 0; pongXmtBuffer_R[i] = 0; }
// Manually Enable Event 0 //CSL_FINST(edma3ccRegs->ESR, EDMA3CC_ESR_E0, SET);
}/* setup_EDMA */
/*---------------------------------------------------------------------------*/ void init_PaRAM_McASP_Rcv_event0 (void) {
Int16 ping_offset_Rcv = (Uint32)pingRcvBuffer_R - (Uint32)pingRcvBuffer_L, pong_offset_Rcv = (Uint32)pongRcvBuffer_R - (Uint32)pongRcvBuffer_L; Int16 ping_c_idx_Rcv = -ping_offset_Rcv + NUM_OF_BYTES_PER_SAMPLE, pong_c_idx_Rcv = -pong_offset_Rcv + NUM_OF_BYTES_PER_SAMPLE;
// Reset EDMA PaRAM OPT Register edma3ccRegs->PARAMSET[EDMA_EVENT2].OPT = CSL_EDMA3CC_OPT_RESETVAL; // Config PaRAM OPT (Enable TC interrupt; Set TCC) edma3ccRegs->PARAMSET[EDMA_EVENT2].OPT = CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) | CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) | CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC = (Uint32) &(mcbsp0Regs->DRR); // (mcaspRegs-> RBUF12); edma3ccRegs->PARAMSET[EDMA_EVENT2].DST = (Uint32) &pingRcvBuffer_L[0];
// Set EDMA Event PaRAM A,B,C CNT edma3ccRegs->PARAMSET[EDMA_EVENT2].A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); edma3ccRegs->PARAMSET[EDMA_EVENT2].CCNT = NUM_OF_SAMPLES_PER_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, ping_offset_Rcv);
// Set EDMA Event PaRAM SRC/DST CIDX edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, ping_c_idx_Rcv);
// Set EDMA Event PaRAM LINK and BCNTRLD edma3ccRegs->PARAMSET[EDMA_EVENT2].LINK_BCNTRLD = CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //2*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*||||||||||||||||||||||||||||||||||||||||| Parameter Set 34 ||||||||||||||||||||||||||||||||||||||*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC interrupt; Set TCC) edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].OPT = CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) | CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) | CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].SRC = (Uint32) &(mcbsp0Regs->DRR); // (mcaspRegs-> RBUF12); edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].DST = (Uint32) &pongRcvBuffer_L[0];
// Set EDMA Event PaRAM A,B,C CNT edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, pong_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, pong_c_idx_Rcv); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].LINK_BCNTRLD = //CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER); // 0080h /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*||||||||||||||||||||||||||||||||||||||||| Parameter Set 36 |||||||||||||||||||||||||||||||||||||||*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC interrupt; Set TCC) edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].OPT = CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) | CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) | CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].SRC = (Uint32) &(mcbsp0Regs->DRR); //(mcaspRegs-> RBUF12); edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].DST = (Uint32) &pingRcvBuffer_L[0];
// Set EDMA Event PaRAM A,B,C CNT edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | // 0000h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, ping_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, ping_c_idx_Rcv); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].LINK_BCNTRLD = CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
}
/*---------------------------------------------------------------------------*/
void init_PaRAM_McASP_Tx_event1 (void) {
Int16 ping_offset_Xmt = (Uint32)pingXmtBuffer_R - (Uint32)pingXmtBuffer_L, pong_offset_Xmt = (Uint32)pongXmtBuffer_R - (Uint32)pongXmtBuffer_L; Int16 ping_c_idx_Xmt = -ping_offset_Xmt + NUM_OF_BYTES_PER_SAMPLE, pong_c_idx_Xmt = -pong_offset_Xmt + NUM_OF_BYTES_PER_SAMPLE;
// this was for event1 // Reset EDMA PaRAM OPT Register edma3ccRegs->PARAMSET[EDMA_EVENT3].OPT = CSL_EDMA3CC_OPT_RESETVAL; // Config PaRAM OPT (Enable TC Interrupt ; Set TCC) edma3ccRegs->PARAMSET[EDMA_EVENT3].OPT = CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) | CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT3);
// Initialize EDMA Event Src and Dst Addresses edma3ccRegs->PARAMSET[EDMA_EVENT3].SRC = (Uint32) pingXmtBuffer_L; //&XmtBuffers_1[0]; // (Uint32)&u32_Xmt_Buffer[0u]; edma3ccRegs->PARAMSET[EDMA_EVENT3].DST = (Uint32) &(mcbsp0Regs->DXR); //(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT edma3ccRegs->PARAMSET[EDMA_EVENT3].A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h edma3ccRegs->PARAMSET[EDMA_EVENT3].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX edma3ccRegs->PARAMSET[EDMA_EVENT3].SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, ping_offset_Xmt) | // //0000h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX edma3ccRegs->PARAMSET[EDMA_EVENT3].SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, ping_c_idx_Xmt) | // 0000h CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD edma3ccRegs->PARAMSET[EDMA_EVENT3].LINK_BCNTRLD = CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*|||||||||||||||||||||||||||||||||||||| Link to parameter set 35 ||||||||||||||||||||||||||||||||||||||*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt; Set TCC) edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].OPT = CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) | CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT3);
// Initialize EDMA Event Src and Dst Addresses edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC = (Uint32) pongXmtBuffer_L; //&XmtBuffers_2[0]; // (Uint32)&u32_Xmt_Buffer[0u]; edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].DST = (Uint32) &(mcbsp0Regs->DXR); //(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, pong_offset_Xmt) | // //0000h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, pong_c_idx_Xmt) | // 0000h CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].LINK_BCNTRLD = CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //2*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/ /*|||||||||||||||||||||||||||||||||||||| Link to parameter set 37 ||||||||||||||||||||||||||||||||||||||*/ /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt; Set TCC) edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].OPT = CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) | CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) | CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT3);
// Initialize EDMA Event Src and Dst Addresses edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC = (Uint32) pingXmtBuffer_L; //&XmtBuffers_1[0]; // (Uint32)&u32_Xmt_Buffer[0u]; edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].DST = (Uint32) &(mcbsp0Regs->DXR); //(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, ping_offset_Xmt) | // //0000h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, ping_c_idx_Xmt) | // 0000h CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].LINK_BCNTRLD = CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34] & 0xFFFFu) | CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2);
}
#include "edma.h"
//#include "mcasp.h"
#include "SignalProcessing.h"
#define EDMA_EVENT0 (Uint8)0u
#define EDMA_EVENT1 (Uint8)1u
#define EDMA_EVENT2 (Uint8)2u //#define EDMA_EVENT0 (Uint8)0u
#define EDMA_EVENT3 (Uint8)3u //#define EDMA_EVENT1 (Uint8)1u
#define EDMA_PARAMETER_SET0 (Uint8)0
#define EDMA_PARAMETER_SET1 (Uint8)1
#define EDMA_PARAMETER_SET32 (Uint8)(32)
#define EDMA_PARAMETER_SET33 (Uint8)(33)
#define EDMA_PARAMETER_SET34 (Uint8)(34)
#define EDMA_PARAMETER_SET35 (Uint8)(35)
extern CSL_McbspRegsOvly mcbsp0Regs;
/*
16.2.3.2.3 Channel Destination Address(DST)
The32-bit destination address parameter specifies the starting byte address of the destination.For DAM
in increment mode,there are no alignment restrictions imposed by EDMA3.For DAM in constant
addressing mode,you must program the destination address to be aligned to a 256-bit aligned address
(5 LSBsofaddressmustbe0).TheEDMA3TC will signal an error, if this rule is violated. See
Section16.2.11.2for additional details.
*/
#pragma DATA_SECTION (pingRcvBuffer_L, ".EdmaData")
Int32 pingRcvBuffer_L[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pingRcvBuffer_R, ".EdmaData")
Int32 pingRcvBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pongRcvBuffer_L, ".EdmaData")
Int32 pongRcvBuffer_L[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pongRcvBuffer_R, ".EdmaData")
Int32 pongRcvBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pingXmtBuffer_L, ".EdmaData")
Int32 pingXmtBuffer_L[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pingXmtBuffer_R, ".EdmaData")
Int32 pingXmtBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pongXmtBuffer_L, ".EdmaData")
Int32 pongXmtBuffer_L[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_SECTION (pongXmtBuffer_R, ".EdmaData")
Int32 pongXmtBuffer_R[NUM_OF_SAMPLES_PER_BUFFER];
Int32 *pingDataPointer, *pongDataPointer;
Uint32 regIPR;
/*#pragma DATA_SECTION(RcvBuffers,"mysection")
#pragma DATA_SECTION(XmtBuffers,"mysection")*/
//Int32 TestData[NUM_OF_SAMPLES_PER_BUFFER*8];
/*
#pragma DATA_ALIGN(pingRcvBuffer_L, 128);
#pragma DATA_ALIGN(pingRcvBuffer_R, 128);
#pragma DATA_ALIGN(pongRcvBuffer_L, 128);
#pragma DATA_ALIGN(pongRcvBuffer_R, 128);
#pragma DATA_ALIGN(pingXmtBuffer_L, 128);
#pragma DATA_ALIGN(pingXmtBuffer_R, 128);
#pragma DATA_ALIGN(pongXmtBuffer_L, 128);
#pragma DATA_ALIGN(pongXmtBuffer_R, 128);
*/
/*
#pragma DATA_ALIGN(TestData, 256);
*/
/*Int32 tone[60] ={ 32768, 32588, 32052, 31164, 29935, 28378, 26510, 24351, 21926, 19261, 16384, 13328, 10126, 6813, 3425,
0, -3425, -6813, -10126, -13328, -16384, -19261, -21926, -24351, -26510, -28378, -29935, -31164, -32052, -32588, -32768,
-32588, -32052, -31164, -29935, -28378, -26510, -24351, -21926, -19261, -16384, -13328, -10126, -6813, -3425, 0, 3425, 6813,
10126, 13328, 16384, 19261, 21926, 24351, 26510, 28378, 29935, 31164, 32052, 32588};
Uint32 tone_pointer = 0;
Int32 TmpBuffer[NUM_OF_SAMPLES_PER_BUFFER];
#pragma DATA_ALIGN(TmpBuffer,8);*/
Uint16 PingPongFlag_Rcv = 1;
Uint16 PingPongFlag_Xmt = 1;
Uint16 i;
Uint8 IntTriggered =1;
extern Int16 interrupt_counter;
extern Int16 run;
extern Uint16 ModeChange;
Int32 *audio_out;
/*---------------------------------------------------------------------------*/
void SetupEDMA (void)
{
Uint16 i;
// Write EMCR, CCEERCLR, ECR registers to clear the EMR, CCERR, ER
// EMCR = 0xFFFFFFFF; CCERRCLR = 0xFFFFFFFF; ECR = 0xFFFFFFFF;
// EDMA event 0-- McASP0 Receiver
// EDMA event 1-- McASP1 Transmitter
// EDMA event 2-- McBSP0 Receiver
// EDMA event 3-- McBSP1 Transmitter
// Clear Event Registers
CSL_FINST(edma3ccRegs->ECR, EDMA3CC_ECR_REG, MASK);
CSL_FINST(edma3ccRegs->SECR, EDMA3CC_SECR_REG, MASK);
//CSL_FINST(edma3ccRegs->IECR, EDMA3CC_IPR_REG, MASK);
//CSL_FINST(edma3ccRegs->ICR, EDMA3CC_IPR_REG, MASK);
edma3ccRegs->ECR = 0xffffffff; // clear events 0 -> 31
edma3ccRegs->SECR = 0xffffffff; // clear secondary events 0 -> 31
edma3ccRegs->IECR = 0xffffffff; // disable all interrupts
edma3ccRegs->ICR = 0xffffffff; // clear all pending interrupts
// Enable Channel 0 - 1 to DSP (Region 1 )
// CSL_FINST(edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE, EDMA3CC_DRAE_E2, ENABLE);
// CSL_FINST(edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE, EDMA3CC_DRAE_E3, ENABLE);
///////////edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE = CSL_FMKT(EDMA3CC_DRAE_E0, ENABLE) | CSL_FMKT(EDMA3CC_DRAE_E1, ENABLE);
edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE = CSL_FMKT(EDMA3CC_DRAE_E2, ENABLE) | CSL_FMKT(EDMA3CC_DRAE_E3, ENABLE);
// Assign Channel 0 - 1 to Queue 0
///////////edma3ccRegs->DMAQNUM[1] = CSL_FMKT(EDMA3CC_DMAQNUM_E0, Q0) | CSL_FMKT(EDMA3CC_DMAQNUM_E1, Q0);
edma3ccRegs->DMAQNUM[0] = CSL_FMKT(EDMA3CC_DMAQNUM_E2, Q0) | CSL_FMKT(EDMA3CC_DMAQNUM_E3, Q0);
// Initialize PaRAM Transfer Context for Events 0 - 1
init_PaRAM_McASP_Rcv_event0();
init_PaRAM_McASP_Tx_event1();
// Enable channel 0 and 1
///////////CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E0, SET); CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E1, SET);
CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E2, SET); CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E3, SET);
// Enable interrupt 0 and 1
CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I2, SET);
///////////CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I0, SET);
//CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I3, SET);
//regIPR = edma3ccRegs->IPR;
//edma3ccRegs->ICR |= 0x00000004;
// Initialize buffers
for(i = 0; i < NUM_OF_SAMPLES_PER_BUFFER; i++)
{
pingRcvBuffer_L[i] = 0; pingRcvBuffer_R[i] = 0;
pongRcvBuffer_L[i] = 0; pongRcvBuffer_R[i] = 0;
pingXmtBuffer_L[i] = 0; pingXmtBuffer_R[i] = 0;
pongXmtBuffer_L[i] = 0; pongXmtBuffer_R[i] = 0;
}
// Manually Enable Event 0
//CSL_FINST(edma3ccRegs->ESR, EDMA3CC_ESR_E0, SET);
}/* setup_EDMA */
/*---------------------------------------------------------------------------*/
void init_PaRAM_McASP_Rcv_event0 (void)
{
Int16 ping_offset_Rcv = (Uint32)pingRcvBuffer_R - (Uint32)pingRcvBuffer_L,
pong_offset_Rcv = (Uint32)pongRcvBuffer_R - (Uint32)pongRcvBuffer_L;
Int16 ping_c_idx_Rcv = -ping_offset_Rcv + NUM_OF_BYTES_PER_SAMPLE,
pong_c_idx_Rcv = -pong_offset_Rcv + NUM_OF_BYTES_PER_SAMPLE;
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_EVENT2].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC interrupt; Set TCC)
edma3ccRegs->PARAMSET[EDMA_EVENT2].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC = (Uint32) &(mcbsp0Regs->DRR); // (mcaspRegs-> RBUF12);
edma3ccRegs->PARAMSET[EDMA_EVENT2].DST = (Uint32) &pingRcvBuffer_L[0];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_EVENT2].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) |
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2);
edma3ccRegs->PARAMSET[EDMA_EVENT2].CCNT = NUM_OF_SAMPLES_PER_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, ping_offset_Rcv);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_EVENT2].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) |
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, ping_c_idx_Rcv);
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_EVENT2].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //2*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*||||||||||||||||||||||||||||||||||||||||| Parameter Set 34 ||||||||||||||||||||||||||||||||||||||*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC interrupt; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].SRC = (Uint32) &(mcbsp0Regs->DRR); // (mcaspRegs-> RBUF12);
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].DST = (Uint32) &pongRcvBuffer_L[0];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) |
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER);
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, pong_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, pong_c_idx_Rcv); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32].LINK_BCNTRLD =
//CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER); // 0080h
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*||||||||||||||||||||||||||||||||||||||||| Parameter Set 36 |||||||||||||||||||||||||||||||||||||||*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC interrupt; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT2);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].SRC = (Uint32) &(mcbsp0Regs->DRR); //(mcaspRegs-> RBUF12);
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].DST = (Uint32) &pingRcvBuffer_L[0];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, ping_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, ping_c_idx_Rcv); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET33].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET32] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
}
/*---------------------------------------------------------------------------*/
void init_PaRAM_McASP_Tx_event1 (void)
{
Int16 ping_offset_Xmt = (Uint32)pingXmtBuffer_R - (Uint32)pingXmtBuffer_L,
pong_offset_Xmt = (Uint32)pongXmtBuffer_R - (Uint32)pongXmtBuffer_L;
Int16 ping_c_idx_Xmt = -ping_offset_Xmt + NUM_OF_BYTES_PER_SAMPLE,
pong_c_idx_Xmt = -pong_offset_Xmt + NUM_OF_BYTES_PER_SAMPLE;
// this was for event1
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_EVENT3].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt ; Set TCC)
edma3ccRegs->PARAMSET[EDMA_EVENT3].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT3);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_EVENT3].SRC = (Uint32) pingXmtBuffer_L; //&XmtBuffers_1[0]; // (Uint32)&u32_Xmt_Buffer[0u];
edma3ccRegs->PARAMSET[EDMA_EVENT3].DST = (Uint32) &(mcbsp0Regs->DXR); //(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_EVENT3].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_EVENT3].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_EVENT3].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, ping_offset_Xmt) | // //0000h
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_EVENT3].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, ping_c_idx_Xmt) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_EVENT3].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*|||||||||||||||||||||||||||||||||||||| Link to parameter set 35 ||||||||||||||||||||||||||||||||||||||*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT3);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC = (Uint32) pongXmtBuffer_L; //&XmtBuffers_2[0]; // (Uint32)&u32_Xmt_Buffer[0u];
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].DST = (Uint32) &(mcbsp0Regs->DXR); //(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, pong_offset_Xmt) | // //0000h
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, pong_c_idx_Xmt) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //2*NUM_OF_SAMPLES_PER_BUFFER);
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*|||||||||||||||||||||||||||||||||||||| Link to parameter set 37 ||||||||||||||||||||||||||||||||||||||*/
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT3);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC = (Uint32) pingXmtBuffer_L; //&XmtBuffers_1[0]; // (Uint32)&u32_Xmt_Buffer[0u];
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].DST = (Uint32) &(mcbsp0Regs->DXR); //(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER);
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER;
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, ping_offset_Xmt) | // //0000h
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, ping_c_idx_Xmt) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2);
}
extern Int32 data_see_1[4000];
interrupt void EDMA3CC_INT1_isr (void)
{
Int32 *data_in_L, *data_in_R;
//float tmp_flt;
Uint16 i, k;
//interrupt_counter += 1; run = 0;
while(edma3ccRegs->IPR != 0){
// Read Interrupt Pending Register
regIPR = edma3ccRegs->IPR;
// Clear Pending Interrupt
////////edma3ccRegs->ICR |= 0x00000001; // MCASP0_Rcv = event 0
// MCBSP0_Rcv = event 2
if (PingPongFlag_Rcv){
data_in_L = pingRcvBuffer_L; data_in_R = pingRcvBuffer_R; audio_out = pingXmtBuffer_R;
if (ModeChange) {
ModeChange = 0;
SigProcInit();
//if (ModeChange==3) ModeChange += 1; else ModeChange = 0;
} else {
StartSigProcessing(data_in_L, data_in_R, audio_out);
}
for (i=0; i<NUM_OF_SAMPLES_PER_BUFFER; i++) {
//data_see_1[i] = data_in_L[i];
pingXmtBuffer_R[i] = data_in_R[i];// beepData[k]; //data_in_L[i];
pingXmtBuffer_L[i] = pingXmtBuffer_R[i]; //beepData[k]; //data_in_L[i];
//k = k +1;
//if (k==BEEP_PERIOD) k = 0;
}
PingPongFlag_Rcv = 0;
} else {
data_in_L = pongRcvBuffer_L; data_in_R = pongRcvBuffer_R; audio_out = pongXmtBuffer_R;
if (ModeChange) {
ModeChange = 0;
SigProcInit();
//if (ModeChange==3) ModeChange += 1; else ModeChange = 0;
} else {
StartSigProcessing(data_in_L, data_in_R, audio_out);
}
for (i=0; i<NUM_OF_SAMPLES_PER_BUFFER; i++) {
//data_see_1[i] = data_in_L[i];
pongXmtBuffer_R[i] = data_in_R[i];//0; //beepData[k];
pongXmtBuffer_L[i] = pongXmtBuffer_R[i]; //
//
//pongXmtBuffer_L[i] = beepData[k]; //data_in_L[i];
//audio_out[i] = (Uint32)beepData[k];
//k = k +1;
//if (k==BEEP_PERIOD) k = 0;
}
PingPongFlag_Rcv = 1;
}
edma3ccRegs->ICR |= 0x00000004;
//edma3ccRegs->ICR |= 0x00000008;
break;
}
}
i attached the code in a file.
regards..