EMIF/SCR priority control for DMA and DSP

Lars Beikirch

Intellectual 615 points

Other Parts Discussed in Thread: TMS320DM6435

Hello all,

I have a question on priority control for EMIF/SCR access by DSP and DMA.

The context:

We use a DM6435 with a FPGA attached to the 8-bit EMIF interface
We transfer a large amount of data from this FPGA to DSP memory by DMA
While this DMA is in progress we would like to read a FPGA register (read 1, 2 or 4 bytes from EMIF) occasionally and very quickly.
Due to FPGA implementation servicing the DMA request blocks the EMIF for approx. 165 µs for each byte because it can't supply the data faster. The FPGA does not block direct register access at all.
The current behaviour: While the DMA transfer is in progress the attempt to access the FPGA register blocks for several milliseconds

From the "EMIF User's Guide" (SPRU984b_emif.pdf, section 2.2) I understood that this behaviour results from the priority control of the SCR. There is written, that "by default DMA has higher priority than DSP". Obviously in our case the EMIF/SCR services mainly the DMA (with big delay because of the blocking behaviour of our FPGA) and only in some rare situations DSP's EMIF access is serviced meanwhile.

I understood that the priority of the DMA can be controled by the Queue priority register (QUEPRI, SPRU987a, section 4.3.1.6). By trial and error I found out that the behaviour of our system changes when I set the DMA prio to 7 (lowest). In that case each byte access by the DSP to an FPGA register is obviously blocked for approx. 165µs - the time the FPGA needs to service a byte request from DMA. It looks like DSP an DMA have the same priority now and share the EMIF in a "round robin" manner. For any other DMA priority the behaviour is always the same as the default described above.

Now my questions:

Where can I find a detailed explanation about the priority control of the EMIF/SCR? Is the EMIF/SCR prio control really based on a byte by byte scheduling or is there any "burst mode" e.g. for reading 4 bytes?
What's the default prio of DSP access to the SCR? (I suppose it's 7.)
How could I change the prio of DSP access to the SCR?

Any help were greatly appreciated.

Thanks, Lars

over 13 years ago

0 RandyP over 13 years ago

TI__Guru* 84110 points

Lars,

The best people to address this may be at the DM64x Forum, so I will put in a request for this thread to be moved there. I do have some comments on the way, though.

Do you really mean microseconds in 165 us? That sounds like a very long time for something that is deterministic and repeatable.

Lars Beikirch said:
Where can I find a detailed explanation about the priority control of the EMIF/SCR?

Unfortunately, we spread the priority registers around to each of the bus masters in the device. I think the DSP's priority settings are in a register with ARB in the name, but some of the other masters may have PRI in the name. Try looking for the DM643x DSP Subsystem Reference Guide to see where it talks about arbitration (ARB) and priority (PRI). Sorry I do not actually know the answers.

I seem to remember a Common Bus Architecture document that may help you understand some of the internal bus architectures we use. I saw one for the C6474, but it may describe similar terms and features as the DM6435.

I think the other questions would be addressed in the DSP Subsystem Reference Guide. It may be that the EDMA uses the same priority as the device that programmed it, so it might not have its own priority setting.

Lars Beikirch said:
Is the EMIF/SCR prio control really based on a byte by byte scheduling or is there any "burst mode" e.g. for reading 4 bytes?

Priority is applied on a VBUS command boundary, which starts to get into a very complex discussion that I am not qualified to lead. The commands depend on how the data is being requested, but continuous bursts can hold off other commands for a long time. So, there is a concept of bursting.

Regards,
RandyP

0 Lars Beikirch over 13 years ago in reply to RandyP

Intellectual 615 points

Hello RandyP,

thanks for your answer and the hints to the documents, I'll check if I find some valuable information there.

RandyP said:
Do you really mean microseconds in 165 us? That sounds like a very long time for something that is deterministic and repeatable.

Yes, I do. Our process providing the data may be so slow in rare cases. The process is deterministic and repeatable on the same input data, but the input data itself are not deterministic and repeatable. Usually the process is faster and provides much more data, thus we use a DMA transfer. And I don't want to have two different mechanisms depending on the data, especially since it will be difficult to predict which case we actually have.

Thanks, Lars

0 Lars Beikirch over 13 years ago in reply to RandyP

Intellectual 615 points

RandyP said:
Try looking for the DM643x DSP Subsystem Reference Guide to see where it talks about arbitration (ARB) and priority (PRI).

I checked it, but didn't find any valuable information.

I found something about "MSTPRI0/1" register, "MDMAARBE.PRI" field and "C64X+ (DMA)" and "C64X+ (CFG) " bus master in the TMS320DM6435 documentation (SPRS344A) and some more information about the "MDMAARBE" in the "TMS320DM643x EDMA3" doc (SPRU987A) and the "TMS320C64x+ DSP Megamodule Reference Guide" (SPRU871H).

Unfortunately I didn't yet get the point:

What are "C64X+ (DMA)" and "C64X+ (CFG) " bus master? What data transfer do they handle?
What's the way when the DSP accesses EMIF?
What does "MDMAARBE.PRI" actually control?

RandyP said:
I seem to remember a Common Bus Architecture document that may help you understand some of the internal bus architectures we use. I saw one for the C6474, but it may describe similar terms and features as the DM6435.

I checked these document too (SPRAAN7 as a rather common document and SPRAX6 and SPRAAW5 for the C6474), but this still didn't answer my questions.

Lars

0 RandyP over 13 years ago in reply to Lars Beikirch

TI__Guru* 84110 points

Lars,

Lars Beikirch said:
I checked it [DM643x DSP Subsystem Reference Guide], but didn't find any valuable information.

It was the first document I found in a search for ARB. Table 9-2 shows the default bus priorities for all the bus masters, and in the notes below the table it names the registers and bit fields that are relevant.

Lars Beikirch said:

What are "C64X+ (DMA)" and "C64X+ (CFG) " bus master? What data transfer do they handle?

What's the way when the DSP accesses EMIF?

The Megamodule Reference Guide explains what the different ports are. It may help to start by studying the block diagram in Figure 1-1 then scrolling down to the text in Section 1.2.10 Extended Memory Controller. The EMIF is one of the "resources outside of the megamodule".

Lars Beikirch said:
What does "MDMAARBE.PRI" actually control?

If two bus commands are available to go through an SCR on the exact same clock cycle (simultaneously generated or pending after waiting on another bus command), the higher priority bus command will be favored for going through next.

We probably do not have answers written exactly the way you are looking for them. These are details that may not have any effect on your results, unfortunately.

In the Training section of TI.com, there is a training video set for the C6474. Even though it is for a different device, the same DSP core is used and the same internal bus architecture is used. It may be helpful for you to review all of the modules. But in particular, the first thre generalized modules may help you understand some of the features of the C64x+ based device architecture. You can find the complete video set here.

Regards,
RandyP

Processors

Processors forum

EMIF/SCR priority control for DMA and DSP