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AM1808 - McASP - Set S/PDIF Clocking Source

Michael Questo
Expert 6000 points
Other Parts Discussed in Thread: AM1808

Hello Freon Champs,

Background:
My customer is using the AM1808 to create an Audio device that utilies the DIT capability of the McASP to acheive an S/PDIF optical out

They've made the necessary modification to the linux kernel (03.20.00.13). Specifically enabling DIT (S/PDIF) output in davinci-mcasp.c and have acheived a recognizable audio out. The issue is that it plays too fast (or too slow, depending on the input sample rate). 

The S/PDIF must transmit data at a clock rate of 128*sample rate.  This clock is either externally sourced (from ACLKX) or internally generated and derived from the high freq clock (AHCLKX). Either way, it's not currently correct. 

What it seems to me we ought to be doing is changing either AHCLKX so we can divide down to a correct out clock or change ACLKX directly. This is the part I am having trouble with and ther doesn't seem to be any support for this in  davinci-mcasp.c.  

Question
How to set either of these clocks to a value of my choosing. 
 
Documentation:
AM1808 TRM:
 
Clocking Overview for McASP:
6.3.6 McASP Clocking
 
McASP Receive/Transmit Clocking Tree
24.2.2.1 Transmit Clock
24.2.2.2 Receive Clock
 
McASP Configuration guide:
24.2.4.1.2 Transmit/Receive Section Initialization
Related Post:


 

  • 0
    TI__Expert 6000 points

    Update:

    They are using a 12Mhz clock (internal?) to source the McASP. The referenced TRM sections describes how to divide a clock but not change its source. The issue is that that frequency doesn't divide down nicely to either 48000*128 or 44100*128. One potential solution is to source another clock that is the correct frequency (or a multiple of the correct frequency) for both 44100 and 48000 sample rates. 

    How do you modifiy the clock source?

  • 0 in reply to Michael Questo
    TI__Expert 6000 points
    Additional Documentation for DIT Operation:
    24.2.4.2.3 Digital Audio Interface Transmit (DIT) Transfer Mode
    24.2.4.2.3.1 Transmit DIT Encoding
    24.2.4.2.3.2 Transmit DIT Clock and Frame Sync Generation --> Contains a summary of all registters required for DIT mode
     
    While operating in DIT mode either AHCLKX can be used to source an external clock or the internal clock (AUXCLK) may be used.  The registers required to divide those sources are described in Section 24.2.2.1 Transmit Clock.
     
    When the internal clock source option is selected, the transmit and receive clocks are derived from the PLL0_AUXCLK which is sourced by PLLC0. 
    Section 7.2 PLL Controllers and Figure 7-1. PLLC Structure describe the registers used to derive/modify the clock..