Query regarding PCB Stack up specification for demo board using DM8107_

Ashok,

I don’t have the exact details for a 4 Layer or 6 Layer board, but they would follow the specifications in the datasheet.  The minimum stackup for routing most of the high speed interfaces is a four-layer stack up, with 6 being the typical number of layers.  If using DDR2 memories it requires 6 layers at a minimum.  Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance, or to reduce the size of the PCB footprint. The device EVM uses 10 layers.

There is some good basic PCB Design information on these wiki pages:
http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design
http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling

Regards,
Marc

Hi Mar. Marc,

We are using DDR3 with your DM8107 Processor.

1. In your EVM Board, we would like to know stack up details used by you.

2. Please provide Fan out details of DM8107 Processor. It would help us in taking vias for 4 layer board stack up.

Hoping for quick response.

Regards,

Ashok

Dear Mr. Marc,

We need following information, please:-

(i) Your EVM board stack up details have the sequence, TOP; GND;VCC; AND BOTTOM layer

where as your PDF FOR  DM8107 Processor states TOP; VCC; GND AND BOTTOM layer;

Which one should I follow?

(ii) Main processor to be positioned on top or bottom side of PCB?

(iii) What is the differential impedance of DDR3 ( e.g clk, dqs.. signals)

(iv) Please provide stack up details used in your PCB ( dielectric thickness and all.........)

Eagerly awaiting for your response.

Regards,

Ashok

Ashok,

Here are answers to your questions:

(i) Your EVM board stack up details have the sequence, TOP; GND;VCC; AND BOTTOM layer where as your PDF FOR  DM8107 Processor states TOP; VCC; GND AND BOTTOM layer; Which one should I follow?
>> The EVM has a different number of layers and a different layer count will drive a different layer sequence.

(ii) Main processor to be positioned on top or bottom side of PCB?
>> Generally, the processor is on top, but either top or bottom is OK.

(iii) What is the differential impedance of DDR3 ( e.g clk, dqs.. signals)
>> Single-ended impedance and differential pair spacing are specifically defined in the DDR routing requirements in the device datasheet.

(iv) Please provide stack up details used in your PCB ( dielectric thickness and all.........)
>> I am looking into this.

Regards,
Marc

Dear Mr. Marc,

We are using your dm8107-dvrrd-rev02a.brd pcb board as reference and my first point was related to this board only.

(i) Above quoteada  board stack up details have the sequence, TOP; GND;VCC; AND BOTTOM layer where as your PDF FOR  DM8107 Processor states TOP; VCC; GND AND BOTTOM layer; Which one should I follow?

(ii) Please provide stack up details used in above quoted PCB ( dielectric thickness and all.........)

Awaiting for response concerned to above quoted pcb.

Regards,

Ashok Malhotra

Ashok,

Sorry for the confusion.  You had asked about the device EVM, so now I understand that you are asking about the DVR Reference Design.  I will look into getting this information for you.

Regards,
Marc

Mr. Ashok,

Please provide more inputs that were requested by Marc to see how we can help here:

“What generated this message? The PCB simulator tool? If so, then I would start with the tool vendor to understand exactly what this message really means. This is also a warning, so it may not be critical. Again the tool vendor should be able to help with that.

When they say “Apart from this, all DDR passed signals also got failed without changing other parameter/specifications with dm8107.ibis” what exactly is meant? Did they pass or not? What parameters were changed? Where were they changed?”

Best Regards

Feroz

Dear Mr Marc/ Feroz,

1) Message was generated by Mentor Graphic simulator tool (Hyper Lynx).

2) By the term "Apart from this", I meant, already DDR passed signals using dm385.ibs got failed when same DDR signals were tried using dm8107.ibs model. Refer Row 172 onwards for DDR signals in attached Excel file.

3) Signals  of TVP 5158, Flash MT29F2G08AADWP, Ethernet I/c RTL8211EG also got failed for signal integrity test when carried out on dm385.ibs as well as dm8107.ibs.

4) While changing above quoted models for processor for testing, parameter related to concerned signals were not modified that is Only assigned processor models were changed to find difference.

5) signals passed or failed; in which field other than required parameters were obtained ; all simulator tool generated outcomes are reflected in attached excel file.

Pl. provide solutions.

Best Regads,

Ashok2134.FEROZmainP-177-001-01-01(SATATYA_HVR-4P)-Si.XLS

Dear Mr. Ashok,

Can you please clarify on below:

Hyperlynx has signal integrity, power integrity, cross talk, etc tools. Are they running crosstalk batch simulation? 

Best Regards

Feroz

Dear Mr. Feroz/Marc,

We are running following selected option:-

(i) Run signal integrity and cross talk simulation on selected nets.

(ii) Run EMC simulation on selected nets.

(iii) Run both audit and batch simulation.

Best Regards,

Ashok Malhotra

Mr. Ashok,

Please see inputs:

          In the report I see failures mainly in rise/fall time, overshoot. Can they tried using the SI oscilloscope where they manually simulate the failing nets, set the proper options for ODT and then measure in the SI oscilloscope. Compare the measured values with datasheet values.

They should have imported the PCB stackup information properly during the simulation setup, identified the signal related power supplies, etc

Best Regards

Feroz

Dear Mr. Feroz/Marc,

PCB stack up, power, model relevant  information are properly set up during simulation. All those failed signals because of overshoot,undershoot, rise time, fall time failure can be manually simulated and checked/verified using oscilloscope.

But there are many signals which do not show any output other than  " ** Warning (severe) ** could not analyse SI; DC operating points not valid, check model thresolds". 

Had there been any reason of failure like other signals, we could have checked in oscilloscope, and could come to certain conclusion.

Signals  of TVP 5158, Flash MT29F2G08AADWP, Ethernet I/c RTL8211EG also got failed for signal integrity test when carried out on dm385.ibs as well as dm8107.ibs.

What is the solution of above quoted failure statement. Please throw some light on it. Pl refer Excel file1680.FEROZmainP-177-001-01-01(SATATYA_HVR-4P)-Si.XLS

best regards,

Hoping quick response.

Ashok

Dear Mr Ashok,

Ok. Could you check with Mentor graphics team as Abhijit had indicated? 

The models for the DM385 and the DM8107 are identical for all signals except the CSI and SATA so they must have done something different in their simulations if they passed with one model but not the other.

Which sub-model did they select when they received the no DC warnings?

Please let us know. 

Best Regards

Feroz

Dear Mr. Feroz/ Marc,

The following sub models are used for :-

(i) H5TQ2G83DFR-PBC_2G (DDR3); ibs model is v69a.ibs

(ii) TVP5158; ibs model is slem001.ibs

(iii) RTL8211EAG; ibs model is RTL8211EG_qfn64_v12.ibs

(iv) MT29F2G08AADWP (Flash); ibs model is m59a.ibs

Best regards,

Ashok

The DM385 models has not really changed any since the initial version, not in the details of the actual  sub models anyhow. Only higher level structure may have changed and would not have anything to do with this warning.

For each pin there are many options for how each pin is configured. When they run the simulations they should be prompted to select which sub-model they would like to simulate with.

We need to know exactly which pins cause this warning and also which sub-model was selected for the use case. We need this in order to be able to determine exactly which sub-model in the device level model is causing issues.

Can we possibly get the log files for this since the error message does not indicate which model caused the issue. Additionally, I thought they still had issues with DDR? The spreadsheet appears clean for DDR.

 Regards

Steve

The pins and the sub models are as mentioned in the attached email. Also excel sheet has this warning put against each of the pins that cause this error.

The following sub models are used for :-

(i) H5TQ2G83DFR-PBC_2G (DDR3); ibs model is v69a.ibs

(ii) TVP5158; ibs model is slem001.ibs

(iii) RTL8211EAG; ibs model is RTL8211EG_qfn64_v12.ibs

(iv) MT29F2G08AADWP (Flash); ibs model is m59a.ibs

More details are at E2e:

RE: Query regarding PCB Stack up specification for demo board using DM8107_

Please do let us know on any further inputs needed here..

Thanks.

Best Regards,

Feroz

Dear Feroz/Marc/Steve,

Some more information  are appended in attached excel file from row 242 onward. 

signal names, pin numbers of DM8107 (U7), TVP5158 (U21), FLASH (U24) and RTL8211EG(U23) are included.

Hope this may become helpful to you.

Regards,

Ashok

3302.FEROZmainP-177-001-01-01(SATATYA_HVR-4P)-Si.XLS

Dear Mr. Ashok,

Can you provide below info and full log for Steve:

The sub-model is not listed for the IOs that generate the warning.

Additionally the warning does not tell us whether it relates to the DM model or the component model. We need to see the full log file.

Thanks & Best Regards

Feroz

Dear Mr. Feroz,

A very small question.

What is full log file.? How and when it gets generated.

Thanks & Best Regards,

Ashok

Dear Mr. Ashok,

What steve would like to know is the sub model option which when run gives these errors. it s not clear form the excel sheet.

So if the Mentor tool generates any log with this info it will be helpful for us to understand the problem. Also mentor support team should be able to explian the issue details. Could you also talk to them please?

Best Regards

Feroz

Dear Mr. Feroz/Marc/Steve,

Mentor tool is not generating any info (log file) other than generating simple single statement of failure in Excel sheet which I have sent to you.

Pl let me know any other kind of support from my end.

Best Regards,

Ashok

Hi Mr. Ashok,

The sub-model is not listed for the IOs that generate the warning.

Additionally the warning does not tell us whether it relates to the DM model or the component model. We need to see the full log file.

Kindly get more inputs from Mentor support team. That will help us understand the issue. Else this is what is used by many of our customers...

Best Regards

Feroz