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PCIe boot from another DSP EVM board via custom backplane

hi,

I'm fighting with PCIe boot from another DSP EVM board via custom backplane.

I have two C6657EVM boards and a custom AMC backplace which completed PCIe communication between RC and EP using the sample soft as below.

C:\ti\pdk_C6657_1_1_2_5\packages\ti\drv\exampleProjects\PCIE_exampleProject

I figured that one C6657EVM(EP side) with PCIe boots from another C6657EVM board(RC side) via custom AMC backplace.

But I can not pass the LINK TRAINING.

I find LOCK bit of register PCIE_SERDES_STS in EP side is still 0 after powered on.

Is there any issues on this C6657evm board?

PS:

I updated the latest IBL on the C6657 board of the EP side and set dipswitches as below.

LENDIAN=1 System is operating in Little Endian mode
BOOT[3:0]=0100 (PCIe boot) 
BOOT4 Reserved =>0
BOOT[8:5]=0000 32bit 
BOOT[9]=0 100MHz
BOOT[12:10]=011 100MHz
PCIESSEN=1 1 = PCIe module enabled
PCIESSMODE[1:0]=00 PCIe in End-point mode

thank you,

bai

  • Bai,

    Each EVM will use its own PCIe reference clock in your custom AMC backplane setup (no common clock provided to EVMs from your backplane), is it correct?

    The IBL update has the workaround for SSC (Spread Spectrum Clocking) support which is needed for the connection between C66x EVM and PC host.

    But in your EVM to EVM setup, if each EVM uses its own PCIe reference clock, the IBL update may cause some issue here.

    Some experiments from our colleges show that we may need to disable the IBL workaround for the EVM to EVM setup.

    The steps are as follows. Please take a look at the README file or source file in the attached example project below.

    1) Disable the PCIe workaround function of the IBL.
    Comment out '#define IBL_ENABLE_PCIE_WORKAROUND 1' in the header file:
    mcsdk_2_xx_xx_xx\tools\boot_loader\ibl\src\device\c665x\target.h
    (Do not set 0 to IBL_ENABLE_PCIE_WORKAROUND but undefine IBL_ENABLE_PCIE_WORKAROUND.)
    2) Rebuild the IBL.
    3) Write the modified IBL to the END POINT SIDE (C6657 #2) of C6657 EVM with the EEPROM writer.

    You can configure the RC side in no boot mode and load the example project to RC.

    On EP side, please rebuild the IBL as above and configure PCIe in PCIe boot mode. 

    The example project has been verified on two C6657 EVM to EVM connection with breakout card. Hope it works for your EVM to EVM with custom backplane as well. 

    8510.PcieBreakOutCardBoot20121220.zip


  • hi Steven.

    My problem has been solved with your advice. Thank you very much.

    I have some additional questions about your advice as follow.

    Could you please teach me?

    1) Program pointer will jump back to the start address of RBL when '#define IBL_ENABLE_PCIE_WORKAROUND 1' is commented out. And RBL will configure PCIe again. In other words, DSP will boot via PCIe directly without IBL,  Am I right?

    2) If 1) is correct, PCIe will use its own reference clock, I figured.  Would you please tell me which register shows this setting.

    3) DoI need SSC when DSP boots from FPGA via Direct PCIe Boot on one board with common clock provided by one OSC?

    4) I can find RBL source code of C6678, but C6657. Would you please tell me where can I get RBL source code of C6657, if possible.

    Thank you.

    bai

  • Bai,

    1. I think you are right that If IBL_ENABLE_PCIE_WORKAROUND is not defined, the IBL will NOT configure PCIe but enter into boot ROM starting address and proceed regular boot ROM code. 

    2. As mentioned in the EVM TRM document, the PCIe reference clock is selected by "PCIe mux control" which is controlled by "SW5[3]" pin. It could be either from the clock generator on board or from the AMC connector.  I think the IBL will overwrite the MUX control to be AMC connector when it detects the EVM is in PCIe boot mode.

    But I am not sure what is the default setup in RBL. It seems to be default setup of the MUX control that the clock is from the board itself.

    3. In the customized board, I do not think we need to use SSC. The two PCIe modules could either use its own reference clock or they could share the same reference clock. Please make sure the reference clock is good and clean.

    4. For the RBL source code, are you referring to the code in the MCSDK boot-loader example folder please?

    I think MCSDK 2.1.1.4 has the code for C6657 as well (C:\ti\mcsdk_2_01_01_04\tools\boot_loader\examples\pcie). Please check the latest MCSDK release. Thanks.

  • hi Steven.

    Thank you for your reply.

    bai

  • Steven,

    I too have a similar application whereby I have a custom PCIe backplane attempting to connect two EVM C6657's together via AMC adaptor boards and PCIe boot one from the other.

    I have downloaded the example provided on this post and modified EVM #2's IBL by disabling IBL_ENABLE_PCIE_WORKAROUND and jumpered as specified within README to boot PCIe-EP.

    I have jumpered EVM #1 as no boot loading/running the example application to configure this EVM #1 as PCIe-RC and connecting to and booting EVM #2 via our custom PCIe backplane.

    I believe I have followed correctly all the steps required to PCIe boot EVM #2 from EVM #1, but it does not go beyond the "link training..." step within main.  No errors are detected up to this point.

    Here's the System_printf() output I see within the console...

    Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Sep  5 2012:17:40:48

    Power domain is already enabled.  You probably re-ran without device reset (which is OK)

    PCIe Power Up.

    PLL configured.

    Successfully configured Outbound Translations!

    Starting link training...

    I have stepped into the function call to pcieWaitLinkUp() and it endlessly loops nevering detecting ltssmState to become pcie_LTSSM_L0.  Each call to the function Pcie_readRegs() within the while loop succeeds, but ltssmState is returned with a value of 3 which I believe is pcie_LTSSM_POLL_COMPLIANCE.  What does this mean?

    Is this the result of an incorrect setup?  Is there something else I can look at that would give me additional insight into what else might be wrong with my configuration?

    I am new to PCIe and this functionality.

    Any help you could provide would be greatly appreciated.

    Thanks,

    -George

  • George,

    It might be something wrong on the EP side. Once you see the RC is stuck at link training loop, could you connect the emulator to the EP EVM and look at the values for the following registers please?

    DEVSTAT (0x02620020) = 0x00011809 to indicate the PCIe is configured in EP mode?

    LOCK bit in PCIE_SERDES_STS (0x0262015C) = 1 to indicate the PLL has been locked?

    Program Counter (PC) register is pointed to L2 SRAM (0x00800xxx) ?

    LTSSM_STATE field in DEBUG0 (0X21801728) = 0x11 to indicate link is up?


    And please make sure the modified IBL has been updated correctly on the EP EVM. There are some steps mentioned in the following post for the IBL update.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/233620/833198.aspx#833198

    And you can also try the peer-to-peer connection mentioned in the original PCIe LLD example. You can configure EP EVM in no boot mode, plug it into the backplane and load the original PCIe LLD example (setup PCIe in EP mode) to EP, with similar setup in RC EVM (no boot mode, plugged into backplane with PCIe LLD example (RC mode) loaded). Then you can run the programs on both sides to see if you could get the link up. It could verify if your hardware setup (i.e. the custom backplane) is good for the PCIe communication.


  • Steven,

    Just to be clear I'm working with C6657 EVM's and the link provided above appears to be for C6670 EVM's.

    I'm using MCSDK_2_01_00_03, PDK_C6657_1_1_0_3 and compiler tools c6000_7.4.1.  Is this OK for this PCIe testing?

    After checking EP side (EVM #2) I see the following which is where my problem is obviously...

    DEVSTAT (0x02620020) = 0x0001080B which suggests that I am still in I2C (IBL).  Correct?

    LOCK bit in PCIE_SERDES_STS (0x0262015C) = 0x00000105

    Program Counter (PC) register is pointing to 0x20B11B54 and not L2 SRAM.  This says it is still in IBL.  Correct?

    LTSSM_STATE field in DEBUG0 (0x21801728) = 0x00002300.

    Obviously, EVM #2 (PCIe-EP) is stuck in IBL for some reason.

    I've reviewed the switch settings and believe them to be correct to boot EVM #2 into PCIe-EP as follows:

    SW3 (1...8)     OFF ON  ON  OFF ON  ON  ON  ON

    SW5 (1...8)     ON  ON  ON  OFF OFF ON  ON  ON

    There was no guidance for PCIESSEN (SW9 Pin 1) so I configured to be enabled as follows.  Correct?

    SW9 (1...2)    OFF ON

    I've followed the re-build instructions of the IBL to disable IBL_ENABLE_PCIE_WORKAROUND and updated EVM #2 using the EEPROM Writer Utility as documented within the C:\ti\mcsdk_2_01_00_03\tools\writer\eeprom\docs\README.txt.  I'm using the app.dat (renamed from i2crom_0x51_c6657_le.dat) following the re-build.

    I've edited eepromwriter_input.txt as follows.  Are the start_addr and swap_data fields correct?

    file_name  = app.dat

    bus_addr   = 0x51

    start_addr = 0

    swap_data  = 0

    I've successfully programmed this new app.dat into EEPROM on EVM #2 using CCS and no-boot option.

    Then running the EVM #1 (PCIe-RC) to EVM #2 (PCIe-EP) test I get the above results which is reason I'm not passing the link training step on PCIe-RC EVM #1.

    After checking further, I've found that there are a few errors in the IBL re-build process that are being ignored as follows:  Is this an issue and possibly why the EVM #2 remains stuck in IBL?  It succeeds in producing "i2crom_0x51_c6657_le.dat" attached below which I rename and use as "app.dat".

    ...

    making device

    make -C ../../device/c64x/make CDEFS='-DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE=ibl_c665x/ibl_init.i2c.be.ccs -DEXE_FILE_1= -DEXE_FILE_2=ibl_c665x/ibl.i2c.be.ccs' device make[5]:

    Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/device/c64x/make'

    q -I -a -ele.oa -o$.da ../../../device/c64x/c64x.s

    /bin/sh: q: command not found

    make[5]: [c64x.da] Error 127 (ignored)

    ...

    What is the "q" command that is failing?  It appears that the error is being ignored and the make proceeds.  Is this important?

    Attached is the make output from the IBL re-build showing this error.  I've also attached the environment settings present following running "source setupenvMsys.sh" within the MINGW32 shell.  NOTE:  I've renamed "setupenvMsys.sh" to "setupenvMsys.sh.txt" here for attachment purposes.

    GenUser@WIN-F9HUBCDRTMG /c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make
    $ make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51
    make -f makestg1 I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 \ENDIAN_MODE=little ARCH=c64x TARGET=c665x EVM=c6657l SPI=no SPI_DEFS='SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1' \CEXCLUDES='COFF BIS NAND_GPIO' c665x
    make[1]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    make -f makestg2 ARCH=c64x TARGET=c665x ENDIAN=little I2C_SIZE_BYTES=0x20000 I2C_BUS_ADDR=0x51 INTERNAL_UTILS= SPI_DEFS='SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1' utils
    make[2]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    make -C ../util/btoccs
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/btoccs'
    make[3]: Nothing to be done for `all'.
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/btoccs'
    make -C ../util/romparse TARGET=c665x
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/romparse'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/romparse'
    make -C ../util/i2cConfig c665x MAINDEFS='-DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE='"ibl_c665x/ibl_init.i2c.be.ccs"' -DEXE_FILE_1='""' -DEXE_FILE_2='"ibl_c665x/ibl.i2c.be.ccs"''
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/i2cConfig'
    make -f makestg2 ARCH=c64x I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 TARGET=c665x c665x
    make[4]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/i2cConfig'
    Checking command line dependencies
    same
    making hw
    make -C ../../hw/c64x/make hw
    make[5]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/hw/c64x/make'
    Checking command line dependencies
    same
    make[5]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/hw/c64x/make'
    making device
    make -C ../../device/c64x/make CDEFS='-DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE=ibl_c665x/ibl_init.i2c.be.ccs -DEXE_FILE_1= -DEXE_FILE_2=ibl_c665x/ibl.i2c.be.ccs' device
    make[5]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/device/c64x/make'
    q -I -a -ele.oa -o$.da ../../../device/c64x/c64x.s
    /bin/sh: q: command not found
    make[5]: [c64x.da] Error 127 (ignored)
    Checking command line dependencies
    same
    make[5]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/device/c64x/make'
    cl6x -z -o i2cparam_c665x_le.out -m i2cparam_c665x_le.map i2cparam.le.oc ../../hw/c64x/make/i2c.le.oc ../../hw/c64x/make/pll.le.oc ../../hw/c64x/make/cfgpll.le.oc ../../hw/c64x/make/cfgpll2.le.oc ../../device/c64x/make/c64x.le.oa ../../hw/c64x/make/psc.le.oc ../../device/c64x/make/c665xutil.le.oc i2cparam.cmd "C:/ti/ccsv5/tools/compiler/c6000_7.4.1"/lib/rts64plus.lib
    <Linking>
    make[4]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/i2cConfig'
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/i2cConfig'
    make -C ../util/bconvert
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/bconvert'
    make[3]: Nothing to be done for `all'.
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/bconvert'
    make -C ../util/iblConfig/build EVM=c6657l I2C_MAP_ADDR=0x500
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/iblConfig/build'
    touch input.txt
    echo "file_name = ibl.bin" > input.txt
    echo "device = 8" >> input.txt
    echo "offset = 0x500" >> input.txt
    echo "ethBoot-doBootp = " >> input.txt
    echo "ethBoot-bootFormat = " >> input.txt
    echo "ethBoot-ipAddr = " >> input.txt
    echo "ethBoot-serverIp = " >> input.txt
    echo "ethBoot-gatewayIp = " >> input.txt
    echo "ethBoot-netmask = " >> input.txt
    echo "ethBoot-fileName = " >> input.txt
    gcc   -O2 -DEVM=c6657l -DI2C_MAP_ADDR=0x500 ./obj/iblConfig.obj ./obj/device.obj  -o iblConfig.out
    cp iblConfig.out iblConfig.out.dbg
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/util/iblConfig/build'
    make[2]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    make -f makestg2 ARCH=c64x TARGET=c665x ENDIAN=little I2C_SIZE_BYTES=0x20000 I2C_BUS_ADDR=0x51 SPI_DEFS='SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1' c665x
    make[2]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    making main SPI_CFG=-DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE="ibl_c665x/ibl_init.i2c.be.ccs" -DEXE_FILE_1="" -DEXE_FILE_2="ibl_c665x/ibl.i2c.be.ccs" CDEFS= EXCLUDES=COFF BIS NAND_GPIO
    make -C ../main/c64x/make CDEFS='-DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE='"ibl_c665x/ibl_init.i2c.be.ccs"' -DEXE_FILE_1='""' -DEXE_FILE_2='"ibl_c665x/ibl.i2c.be.ccs"'' main
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/main/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/main/c64x/make'
    making device SPI_CFG=-DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE="ibl_c665x/ibl_init.i2c.be.ccs" -DEXE_FILE_1="" -DEXE_FILE_2="ibl_c665x/ibl.i2c.be.ccs" CDEFS= EXCLUDES=COFF BIS NAND_GPIO
    make -C ../device/c64x/make CDEFS='-DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DSPI_MODE=1 -DSPI_ADDR_WIDTH=24-DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE='"ibl_c665x/ibl_init.i2c.be.ccs"' -DEXE_FILE_1='""' -DEXE_FILE_2='"ibl_c665x/ibl.i2c.be.ccs"'' device
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/device/c64x/make'
    q -I -a -ele.oa -o$.da ../../../device/c64x/c64x.s
    /bin/sh: q: command not found
    make[3]: [c64x.da] Error 127 (ignored)
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/device/c64x/make'
    making ethboot
    make -C ../ethboot/c64x/make ethboot
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/ethboot/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/ethboot/c64x/make'
    making nandboot
    make -C ../nandboot/c64x/make nandboot
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/nandboot/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/nandboot/c64x/make'
    making driver
    make -C ../driver/c64x/make driver
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/driver/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/driver/c64x/make'
    making hw
    make -C ../hw/c64x/make hw
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/hw/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/hw/c64x/make'
    making interp
    make -C ../interp/c64x/make interp
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/interp/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/interp/c64x/make'
    making ecc
    make -C ../ecc/c64x/make ecc
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/ecc/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/ecc/c64x/make'
    making norboot
    make -C ../norboot/c64x/make norboot
    make[3]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/norboot/c64x/make'
    Checking command line dependencies
    same
    make[3]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/norboot/c64x/make'
    cat ibl_c665x/ibl_init_objs_template.inc | sed -e s/ENDIAN_TAG/le/g > ibl_c665x/ibl_init_objs.tmp
    cl6x -ppo -DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DENDIAN_TAG=le ibl_c665x/ibl_init_objs.tmp
    cp -f ibl_c665x/ibl_init_objs.pp ibl_c665x/ibl_init_objs.inc
    cl6x -z -o ibl_c665x/ibl_c665x_init.out -m ibl_c665x/ibl_c665x_init.map ibl_c665x/ibl_init.cmd "C:/ti/ccsv5/tools/compiler/c6000_7.4.1"/lib/rts64plus.lib
    <Linking>
    cp -f ibl_c665x/ibl_c665x_init.out ibl_c665x/ibl_c665x_init.le.out
    rm -f -f ibl_c665x/ibl_init_obj.inc
    hex6x -order L ibl_c665x/ibl_init_image.rmd ibl_c665x/ibl_c665x_init.out
    Translating to ASCII-Hex format...
       "ibl_c665x/ibl_c665x_init.out"   ==> .text
       "ibl_c665x/ibl_c665x_init.out"   ==> .cinit
       "ibl_c665x/ibl_c665x_init.out"   ==> .const
    cp -f ibl_le.b ibl_c665x/ibl.b
    ../util/btoccs/b2ccs ibl_c665x/ibl.b ibl_c665x/ibl_init.le.ccs
    hex6x -order L ibl_c665x/ibl_init.rmd ibl_c665x/ibl_c665x_init.out
    Translating to ASCII-Hex format...
       "ibl_c665x/ibl_c665x_init.out"   ==> .cinit  (BOOT LOAD)
       "ibl_c665x/ibl_c665x_init.out"   ==> .const  (BOOT LOAD)
       "ibl_c665x/ibl_c665x_init.out"   ==> .text   (BOOT LOAD)
    ../util/bconvert/bconvert64x -le ibl_le.b ibl.b
    cp -f ibl.b ibl_c665x
    ../util/btoccs/b2i2c ibl_c665x/ibl.b ibl_c665x/ibl.i2c.b
    ../util/btoccs/b2ccs ibl_c665x/ibl.i2c.b ibl_c665x/ibl_init.i2c.le.ccs
    sed -e 's/\r//' ../util/symExtract/symExtract > ../util/symExtract/symExtract_unix
    bash ../util/symExtract/symExtract_unix ibl_c665x/ibl_c665x_init.map ibl_c665x/ibl_init_symbols.inc iblBootBtbl iblMalloc iblFree iblMemset iblMemcpy
    rm -f ../util/symExtract/symExtract_unix
    cat ibl_c665x/ibl_objs_template.inc | sed -e s/ENDIAN_TAG/le/g > ibl_c665x/ibl_objs.tmp
    cl6x -ppo -DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=0x51 -DEXCLUDE_COFF -DEXCLUDE_BIS -DEXCLUDE_NAND_GPIO -DENDIAN_TAG=le ibl_c665x/ibl_objs.tmp
    cp -f ibl_c665x/ibl_objs.pp ibl_c665x/ibl_objs.inc
    cl6x -z -o ibl_c665x/ibl_c665x.out -m ibl_c665x/ibl_c665x.le.map  ibl_c665x/ibl.cmd "C:/ti/ccsv5/tools/compiler/c6000_7.4.1"/lib/rts64plus.lib
    <Linking>
    cp -f ibl_c665x/ibl_c665x.out ibl_c665x/ibl_c665x.le.out
    rm -f -f ibl_c665x/ibl_obj.inc
    hex6x -order L ibl_c665x/ibl.rmd ibl_c665x/ibl_c665x.out
    Translating to ASCII-Hex format...
       "ibl_c665x/ibl_c665x.out"   ==> .cinit       (BOOT LOAD)
       "ibl_c665x/ibl_c665x.out"   ==> .const       (BOOT LOAD)
       "ibl_c665x/ibl_c665x.out"   ==> .text        (BOOT LOAD)
       "ibl_c665x/ibl_c665x.out"   ==> .switch      (BOOT LOAD)
    ../util/bconvert/bconvert64x -le ibl_le.b ibl.b
    cp -f ibl.b ibl_c665x
    ../util/btoccs/b2i2c ibl_c665x/ibl.b ibl_c665x/ibl.i2c.b
    ../util/btoccs/b2ccs ibl_c665x/ibl.i2c.b ibl_c665x/ibl.i2c.le.ccs
    make[2]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    make -f makestg2 ARCH=c64x TARGET=c665x I2CROM=little_endian I2C_BUS_ADDR=0x51 I2C_MAP_ADDRESS= EVM=c6657l COMPACT_I2C= SPI_DEFS='SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1'  i2crom spiRom
    make[2]: Entering directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    cl6x -ppo -I../cfg/c665x -DI2C_BUS_ADDR=0x51 -DI2C_MAP_ADDR=0x500 -DEVM=c6657l -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE='"ibl_c665x/ibl_init.i2c.le.ccs"' -DEXE_FILE_1='"ibl_c665x/ibl.i2c.le.ccs"' -DEXE_FILE_2='""' ibl_c665x/i2crom.map.pre
    ../util/romparse/romparse  -rom_base 0x51 ibl_c665x/i2crom.map.pp
    file_cp -f i2crom.ccs ibl_c665x/i2crom.ccs
    cp -f i2crom.ccs ibl_c665x/i2crom.dat
    ../util/btoccs/ccs2bin -swap ibl_c665x/i2crom.ccs ibl_c665x/i2crom.bin
    cp ibl_c665x/i2crom.bin ../util/iblConfig/build/ibl.bin
    (cd ../util/iblConfig/build;./iblConfig.out)
    Opened file ibl.bin
    Generated updated binary ibl.bin
    cp ../util/iblConfig/build/ibl.bin ibl_c665x/i2crom.bin
    rm -f i2crom.ccs ibl_le.b ibl.b
    Making SPI ROM
    cl6x -ppo -I../cfg/c665x -DSPI_MODE=1 -DSPI_ADDR_WIDTH=24 -DSPI_NPIN=5 -DSPI_CSEL=2 -DSPI_C2TDEL=1 -DSPI_CLKDIV=8 -DSPI_ROM=1 -DPAD_FILE_ID_1=1 -DPAD_FILE_ID_2=1 -DINIT_EXE_FILE='"ibl_c665x/ibl_init.i2c.le.ccs"' -DEXE_FILE_1='"ibl_c665x/ibl.i2c.le.ccs"' -DEXE_FILE_2='""' ibl_c665x/spiRom.map.pre
    ../util/romparse/romparse  -fill 0xff -rom_base 0 ibl_c665x/spiRom.map.pp
    file_cp -f i2crom.ccs ibl_c665x/spiRom.ccs
    cp -f i2crom.ccs ibl_c665x/spiRom.dat
    make[2]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    make[1]: Leaving directory `/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make'
    cp -f ibl_c665x/i2crom.dat bin/i2crom_0x51_c6657_le.dat
    cp -f ibl_c665x/i2crom.bin bin/i2crom_0x51_c6657_le.bin
    cp -f ../util/i2cConfig/i2cparam_c665x_le.out bin/i2cparam_0x51_c6657_le_0x500.out
    

    GenUser@WIN-F9HUBCDRTMG /c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make
    $ source setupenvMsys.sh
    
    GenUser@WIN-F9HUBCDRTMG /c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make
    $ set
    !::='::\'
    !C:='C:\MinGW\msys\1.0\bin'
    ALLUSERSPROFILE='C:\ProgramData'
    APPDATA='C:\Users\GenUser\AppData\Roaming'
    BASH=/usr/bin/sh
    BASH_ARGC=()
    BASH_ARGV=()
    BASH_LINENO=()
    BASH_SOURCE=()
    BASH_VERSINFO=([0]="3" [1]="1" [2]="17" [3]="1" [4]="release" [5]="i686-pc-msys")
    BASH_VERSION='3.1.17(1)-release'
    C6X_BASE_DIR='"C:/ti/ccsv5/tools/compiler/c6000_7.4.1"'
    C6X_BASE_DIR_MSYS=/c/ti/ccsv5/tools/compiler/c6000_7.4.1
    COLUMNS=80
    COMMONPROGRAMFILES='C:\Program Files (x86)\Common Files'
    COMMONPROGRAMFILES(X86)='C:\Program Files (x86)\Common Files'
    COMMONPROGRAMW6432='C:\Program Files\Common Files'
    COMPUTERNAME=WIN-F9HUBCDRTMG
    COMSPEC='C:\Windows\SysWOW64\cmd.exe'
    DIRSTACK=()
    DSS_SCRIPT_DIR='"C:\ti\ccsv5\ccs_base\scripting\bin"'
    EUID=500
    FP_NO_HOST_CHECK=NO
    GROUPS=()
    HISTFILE=/home/GenUser/.bash_history
    HISTFILESIZE=500
    HISTSIZE=500
    HOME=/home/GenUser
    HOMEDRIVE=C:
    HOMEPATH='\'
    HOSTNAME=WIN-F9HUBCDRTMG
    HOSTTYPE=i686
    I2C_BUS_ADDR=0x50
    IFS='
    '
    LINES=25
    LOCALAPPDATA='C:\Users\GenUser\AppData\Local'
    LOGNAME=GenUser
    LOGONSERVER='\\WIN-F9HUBCDRTMG'
    MACHTYPE=i686-pc-msys
    MAILCHECK=60
    MAKE_MODE=unix
    MPCONFIG_APPDATAROOT='C:\ProgramData'
    MPCONFIG_PRODUCTAPPDATAPATH='c:\ProgramData\Microsoft\Microsoft Antimalware'
    MPCONFIG_PRODUCTCODENAME=Torino
    MPCONFIG_PRODUCTPATH='c:\Program Files\Microsoft Security Client\Antimalware'
    MPCONFIG_PRODUCTUSERAPPDATAPATH='C:\Users\GenUser\AppData\Local\Microsoft\Microsoft Antimalware'
    MPCONFIG_REPORTINGGUID=B1D02059-D84B-46A6-B36C-0743BE235E7E
    MSYSCON=sh.exe
    MSYSTEM=MINGW32
    NUMBER_OF_PROCESSORS=2
    OLDPWD=/c
    OPTERR=1
    OPTIND=1
    OS=Windows_NT
    OSTYPE=msys
    PATH='.:/usr/local/bin:/mingw/bin:/bin:/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin:/c/ti/xdctools_3_23_02_47:/c/Windows/system32:/c/Windows:/c/Windows/System32/Wbem:/c/Windows/System32/WindowsPowerShell/v1.0/:/c/Program Files(x86)/Microsoft SQL Server/100/Tools/Binn/:/c/Program Files/Microsoft SQL Server/100/Tools/Binn/:/c/Program Files/Microsoft SQL Server/100/DTS/Binn/:/c/Python27:/c/ti/ccsv5/tools/compiler/c6000_7.4.1/bin:/mingw/bin:/c/ti/xdctools_3_23_02_47:/c/ti/ccsv5/tools/compiler/c6000_7.4.1/bin'
    PATHEXT='.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC'
    PIPESTATUS=([0]="0")
    POSIXLY_CORRECT=y
    PPID=1
    PROCESSOR_ARCHITECTURE=x86
    PROCESSOR_ARCHITEW6432=AMD64
    PROCESSOR_IDENTIFIER='Intel64 Family 6 Model 44 Stepping 2, GenuineIntel'
    PROCESSOR_LEVEL=6
    PROCESSOR_REVISION=2c02
    PROGRAMDATA='C:\ProgramData'
    PROGRAMFILES='C:\Program Files (x86)'
    PROGRAMFILES(X86)='C:\Program Files (x86)'
    PROGRAMW6432='C:\Program Files'
    PROMPT='$P$G'
    PS1='\[\033]0;$MSYSTEM:\w\007
    \033[32m\]\u@\h \[\033[33m\w\033[0m\]
    $ '
    PS2='> '
    PS4='+ '
    PSMODULEPATH='C:\Windows\system32\WindowsPowerShell\v1.0\Modules\'
    PUBLIC='C:\Users\Public'
    PWD=/c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make
    SESSIONNAME=Console
    SHELL=/bin/sh
    SHELLOPTS=braceexpand:emacs:hashall:histexpand:history:interactive-comments:monitor:posix
    SHLVL=1
    SYSTEMDRIVE=C:
    SYSTEMROOT='C:\Windows'
    TARGET=c665x
    TEMP=/tmp
    TERM=cygwin
    TMP=/tmp
    TOOLSC6X='"C:/ti/ccsv5/tools/compiler/c6000_7.4.1"'
    TOOLSC6XDOS='"C:/ti/ccsv5/tools/compiler/c6000_7.4.1"'
    UID=500
    USERDOMAIN=WIN-F9HUBCDRTMG
    USERNAME=GenUser
    USERPROFILE='C:\Users\GenUser'
    VS100COMNTOOLS='C:\Program Files (x86)\Microsoft Visual Studio 10.0\Common7\Tools\'
    WINDIR='C:\Windows'
    XDCROOT=C:/ti/xdctools_3_23_02_47
    _=setupenvMsys.sh
    i='/etc/profile.d/*.sh'
    

    2727.i2crom_0x51_c6657_le.dat 

     

    I haven't yet tried the PCIe LLD example and discretely loading both EVM's explicitly.  Before I did that I was hoping you might see why what I'm trying is failing.

    Thanks,

    -George

  • hi Steven,

    I pass the pcie directly boot by using the sample. But I still wonder how to make ddrInitCode[ ] and what is the data structure of it.

    Because I noticed that RC side pushed the ddrInitCode[ ] to EP side by 3 times.

    Need I to do the same?

    If I push an ordinary binary code to DDR3 area and start it from MAGIC ADDRESS, might it work?

    Thank you

    bai

  • George,

    My colleague did some experiments on C6657LE EVM and he could see the same IBL build error message as you saw. There are two options in the EEPROM writer, .dat file or .bin file. My colleague noticed that the writing of data format to EEPROM may fail sometimes although the EEPROM writer did not give any error. But the writing the binary format to the EVM seems to be correct all the time. 

    So please give a try with the binary format with EEPROM writer. You can also try the attached IBL binary file (renamed as .txt for attachment purpose) which has the PCIe workaround disabled and has been verified on the PCIe boot test with two 6657 EVMs and breakout card. Hope it could work for you as well.

    @(Qd�@(Qd�@(Qd�@(Qd�@(Qd�@(Qd�@(Qd�@(Qd�Q;�Q����Q����(5=��zGb�0x3�q0���U�!pQ����d����������������������������@@
    ��0
    � ����������c6657-le.binp�JV�.���0 ���������������������t��o�X���������������/�����/��}�|�1�
     �	�4�8��$�@�����H�@���������$�����p���$`�$ �p�����h�!��&4�&��&X�/`0 ���	)�((���#b�	��b�B��b�����G���o1�g�G�
    �	��c�� �	�����n0c��p���]�(��@��w��[P(^*��Y�0g`����3(�Y�s��"N��,��YF &�:��*�@R("� ����k��� LE'c[c[�Fc[%'�Z���<<�[�n � o�
    ��b���
    �@�2("� ��Z�(���@����d'� G�φ�E��[�����¥� � �@���@�`�`̀������������$���[��G����� �IJP ���␈� �@�@�`���`ĀĀ̠������ऒ������������(���(����H�H���$h���hĈĈ̨��������������I�Ą�P�� ��� �@�@�`����J�`ĀĀ̠����������������ऒ2�D'p�`��GC��[��Q��!������!�GA��Q�DL!L��!D��AL��"�zj.AD�2���[@`DL#L�[�#D�⤌!L�G���!D�#.������R�����[ `DL#L�[�[#D�n
    CDCLcL�[�[cD�⤒�D�L�L�[�D��c.���[D'��"��[����["��B�BĞk	R��g'	"7F��0y��"A�����x�!R Bq��20� {�@
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    xFn���G�vv���GLvv�e��O�X���vt� G�X������� �#�2�""px	y㠂����G	�y�� z
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    file_name  = app.bin
    bus_addr   = 0x51
    start_addr = 0
    swap_data  = 0
    
    
    
    
    

    2642.log.txt

  • Bai,

    I think the breakout card example is derived from the PCIe boot example mentioned in the README file of C:\ti\mcsdk_2_01_xx\tools\boot_loader\examples\pcie\docs.

    It uses the RC EVM instead of the Linux host to write boot table into the PCIe EP EVM, write entry point to Magic address and send interrupt to EP for the boot.

    The ddrInitCode is DDR Init Boot Image mentioned in section 4 in the README file. It is originally in .out format and is converted to a header file with array of the image data, by the tools of "hex6x.exe","bttbl2hfile.exe" and "hfile2array.exe".

    The "pushData()" in the "pcie_sample.c" is derived from the "pushData()" in "pciedemo.c" in "C:\ti\mcsdk_2_01_xx\tools\boot_loader\examples\pcie\linux_host_loader".

    It seems the DDR init header file array has the entry address in the front and the size of code and then the actual code. You can take a look the code of this API to see how the host/RC tries to push the boot image into the EP DSP memory.

    I think if you would like to take advantage of these boot tools in your application, you should follow the same procedure. You can have your own application and you could convert it into the image file and push to the DSP device for boot. 

    You can take a look at README file (e.g. section 9.3 HelloWorld example) to see how these demos are working. Hope it helps.

  • Steven,

    I tried updating EVM #2 with *my* "app.bin" instead of "app.dat".  This did *not* fix the problem.  I witness the same problem of not passing "link training..."  I did notice that my "app.bin" was considerably smaller (4 KB) whereas the "app.bin" provided by you was considerably larger (47 KB).  I believe that there must be something wrong in my re-building of the IBL.  I'm using mcsdk_2_01_00_03, pdk_C6657_1_1_0_3, and compiler C6000_7.4.1.  Is this OK?

    Here's my "app.dat" and "app.bin" which do NOT work...  Why?  I provided "make" process output of my re-build on prior posting.  What is wrong?  I would definitely want to be able to perform this IBL re-build on my end to verify that I could actually perform this step successfully.  Please help me understand this.

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    ��0
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    I then tried the modified IBL "app.bin" provided by you in EVM #2 and viola it success!

    What versions of the mcsdk, pdk, and compiler were used to produce your IBL "app.bin"?

    Here's the console output from EVM #2 during EEPROM IBL update...  Notice the ~47 KB app size being programmed which is 40 KB larger than my version

    EEPROM Writer Utility Version 01.00.00.05

    Writing 47080 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0051 starting from device address 0x0000 ...

    Reading 47080 bytes from EEPROM bus address 0x0051 to DSP memory address 0x0c010000 starting from device address 0x0000 ...

    Verifying data read ...

    EEPROM programming completed successfully

    After programming your "app.bin" into EVM #2 I was able to successfully run the EVM to EVM PCIe test and boot PCIe-EP (EVM #2) from PCIe-RC (EVM #1) using our custom PCIe backplane.  I did step into the function pcieWaitLinkUp() on EVM #1 and did see 17 (pcie_LTSSM_L0) being achieved.

    Here's the console output from EVM #1 (PCIe-RC)

    Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Sep  5 2012:17:40:48

    Power domain is already enabled.  You probably re-ran without device reset (which is OK)

    PCIe Power Up.

    PLL configured.

    Successfully configured Outbound Translations!

    Starting link training...

    Link is up.

    [Core0 L2] 10820000: 53504 bytes

    Pushing data (60820000) ...

    [Core0 L2] 1083066C: 352 bytes

    Pushing data (6083066C) ...

    [Core0 L2] 108301C0: 492 bytes

    Pushing data (608301C0) ...

    Entry: 1082C9A0

    [DDR3    ] 80000000: 54048 bytes

    Pushing data (61800000) ...

    [DDR3    ] 8000E3E8: 635 bytes

    Pushing data (6180E3E8) ...

    [DDR3    ] 8000E664: 364 bytes

    Pushing data (6180E664) ...

    Entry: 8000CB00

    Test Completed!

    Here's the RS-232 terminal output from EVM #2

    PCIE Boot Hello World Example Version 01.00.00.00

    Booting Hello World image on Core 0 from PCIE ...

    Booting Hello World image on Core 1 from Core 0 ...

    I then connected CCS/JTAG to EVM #2 and checked the following and obtained these values per your prior post...

    DEVSTAT (0x02620020) = 0x00011809 ... indicating PCIe is configured in EP mode

    PCIE_SERDES_STS (0x0262015C) = 1 ... LOCK bit indicating the PLL has been locked

    Program Counter (PC)  = 0x80009A84 ... DDR3 memory

    DEBUG0 (0X21801728) = 0x0300B711 ... LTSSM_STATE field indicates link is up

    All looks to be in order now.

    I'd like to understand why I can't re-build IBL to disable IBL_ENABLE_PCIE_WORKAROUND.

    Any ideas as to what I'm doing wrong?  Being able to perform this on my end would be appreciated.

    Thanks for the help in getting this to work.  This has verified that my EVM to EVM PCIe setup and custom PCIe backplane works.

    -George

     

  • George,

    Have you compared your "make_output.txt" with my colleague's "log.txt" (posted with example app.bin before) please?

    It looks like he was using MCSDK 2.1.0.3 as well. But your process file shows that you had lots of original things in your IBL folders that they were not rebuilt.

    I am wondering if it will make difference to do "make clean" first (remove the original copies) and then issue the make command for IBL rebuild.

  • Steven,

    I did look at your colleague's "log.txt" and I do see the "q" command not found as I'm seeing.

    In an attempt to create a re-built IBL on my system equivalent to the one you provided, I've performed a "make clean" followed by a "make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51" and I'm still getting the same small 4 K-Byte file i2crom_0x51_c6657_le.bin.  Loading this re-built IBL into EEPROM does not work when booting EVM #2 as PCIe-EP in my test.  EVM #1 (PCIe-RC) fails "link training".

    I've tried to capture all the screen output from the make process but "warnings", "sed", and other "missing command 'q'" output doesn't get re-directed to my output log file, but rather to the MINGW32 console itself.

    I'm using the following command for make with screen output re-direction which isn't quite correct in capturing all output somehow...

    make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51 > MyMakeLog.txt

    How can I get all the screen output from make to be re-directed into the file MyMakeLog.txt?

    Having this I then can do a direct compare with the "log.txt" file you've provided with mine to see what might be going wrong.

    -George

  • Steven,

    I know now how to have ALL "make" console output (stdout and stderr) re-directed to the same make.log file.  Here's how it's done for both the "clean" and the desired IBL re-build makes.  FYI, mingw is using a DOS/NT command shell and its re-direction syntax is as documented here http://www.robvanderwoude.com/redirection.php...

    make clean 1> MyMakeCleanLog.txt 2>&1

    make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51 1> MyMakeLog.txt 2>&1

    Here are the two make output logs...

    3632.MyMakeCleanLog.txt

    6874.MyMakeLog.txt 

    Upon comparing "MyMakeLog.txt" with your colleague's "log.txt" I found them to be absolutely identical, yet my resulting "i2crom_0x51_c6657_le.bin" being generated is only 4 KBytes.  I've attached my build results here with .txt extensions for your reference.

    6087.i2cparam_0x51_c6657_le_0x500.out.txt

    @(Qd�@(Qd�@(Qd�@(Qd�@(Qd�@(Qd�@(Qd�@(Qd�QQ����Q����(5=��zGb�0x3�q0���U�!pQ����d����������������������������@@
    ��0
    � ����������c6657-le.binp��.���0 ���������������������t�X���������������/�����/�|�1�
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    At the moment I'm at a loss to explain why my "app.bin" is so much smaller (~4 KB) than the one that your colleague has provided (~47 KB).

    Is there something else that needs to be done to re-build IBL other than the following two steps?  If so, what?

    1) Comment out '#define IBL_ENABLE_PCIE_WORKAROUND 1' in the header file...

    mcsdk_2_01_00_03\tools\boot_loader\ibl\src\device\c665x\target.h

    2) Rebuild IBL...

    cd /c/ti/mcsdk_2_01_00_03/tools/boot_loader/ibl/src/make

    make clean

    make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51 1> MyMakeLog.txt 2>&1

    Why is my resulting "app.bin" small and obviously incorrect?

    -George

     

  • George,

    I installed MinGW in my local PC and tried to rebuild the IBL as well.

    I am using MCSDK 2.1.2.5 and C6000 compiler 7.4.2.

    The steps are just as yours except I have to modify the TI compiler path in the SH file, but I think you did that as well.

    The bin file I generated is about 47KB. So I could not reproduce what you observed in your setup.

    1) Comment out '#define IBL_ENABLE_PCIE_WORKAROUND 1' in the header file...

    mcsdk_2_01_02_05\tools\boot_loader\ibl\src\device\c665x\target.h

    2) modify setupenvMsys.sh for compiler path

    On a MinGW-MSYS Bash shell

    "cd /c/ti/mcsdk_2_01_02_05/tools/boot_loader/ibl/src/make"

    "source setupenvMsys.sh"

    3) Rebuild IBL...

    make clean

    make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51 1> MyMakeLog.txt 2>&1

    I uploaded the log file and the SH file I am using. It looks like the log file is similar as yours except the compiler/MCSDK version. 

    I think you can install the latest MCSDK and try to re-build again in a fresh environment to see if it could fix the issue.

     1031.MyMakeLog.txt

    #!/bin/bash
    
    # Environment setup to be done if using MSYS Bash shell for build
    
    # Specify the base directory of the c6000 compiler with UNIX style path separator
    export C6X_BASE_DIR='"C:/ti/ccsv5/tools/compiler/c6000_7.4.2"'
    
    # Specify the base directory of the c6000 compiler in format understandable by the MSYS Bash shell 
    export C6X_BASE_DIR_MSYS=/c/ti/ccsv5/tools/compiler/c6000_7\.4\.2
    
    # Don't modify the below variables. They are derived from the above definitions 
    export PATH=$PATH:$C6X_BASE_DIR_MSYS/bin
    export TOOLSC6X=$C6X_BASE_DIR
    export TOOLSC6XDOS=$C6X_BASE_DIR
    
    

  • Steven,

    Thanks for the help.  I have re-built the IBL successfully and it now allows EVM #2 (PCIe-EP) to establish a valid PCIe connection with EVM #1 (PCIe-RC).

    I installed the latest mcsdk_2_01_02_05, disabled IBL_ENABLE_PCIE_WORKAROUND within target.h, re-built IBL, and updated EEPROM on EVM #2 via epromwriter.  NOTE: I did not update to latest cgt_7.4.2 and used cgt_7.4.1.  This says that the issue preventing a successful re-build of IBL was solely due to my older mcsdk_2.01_00_03 and not the version of the compiler.  There must be a problem within the older mcsdk_2_01_00_03.

    Here's the log following "make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51 1>MyMakeLog.txt 2>&1"

    3058.MyMakeLog.txt

    Here's the epromwriter console output on EVM #2 (PCIe-EP) showing the larger ~47KB size.

    [C66xx_0] EEPROM Writer Utility Version 01.00.00.05

    Writing 47080 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0051 starting from device address 0x0000 ...

    Reading 47080 bytes from EEPROM bus address 0x0051 to DSP memory address 0x0c010000 starting from device address 0x0000 ...

    Verifying data read ...

    EEPROM programming completed successfully

    Here's the successful console output from EVM #1 (PCIe-RC)...

    Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Sep  5 2012:17:40:48

    Power domain is already enabled.  You probably re-ran without device reset (which is OK)

    PCIe Power Up.

    PLL configured.

    Successfully configured Outbound Translations!

    Starting link training...

    Link is up.

    [Core0 L2] 10820000: 53504 bytes

    Pushing data (60820000) ...

    [Core0 L2] 1083066C: 352 bytes

    Pushing data (6083066C) ...

    [Core0 L2] 108301C0: 492 bytes

    Pushing data (608301C0) ...

    Entry: 1082C9A0

    [DDR3    ] 80000000: 54048 bytes

    Pushing data (61800000) ...

    [DDR3    ] 8000E3E8: 635 bytes

    Pushing data (6180E3E8) ...

    [DDR3    ] 8000E664: 364 bytes

    Pushing data (6180E664) ...

    Entry: 8000CB00

    Test Completed!

     

    Thanks for helping me create a valid re-built IBL.

    -George