Megamodule memory protection

TS,

Which DSP are you using?

What values are you writing to these registers?

Do you read back the correct values from the registers to confirm they were programmed correctly?

Is the memory protection occurring and you are concerned about not getting the exception triggered? Or is the memory protection failing and the value written does appear in the protected memory?

Which bus master is writing to the memory?

Regards,
RandyP

The DSP is one of those... OK,DSKTCI6482 - Spectrum Digital.

Anyway, To my understanding this is about Megamodule - standard, except
that only upper parts of LiP and L1D exist. (MPPAs 16 - 31) and
only lower part of L2 exists (MPPAs 0 - 31).

The register values after configuration:


EVTMASK_0    0002000F
EVTMASK_1    00000000
EVTMASK_2    00000018
EVTMASK_3    00000000

EXPMASK_0    FFFFFDFF    // AET event
EXPMASK_1    FFFFFFFF
EXPMASK_2    FFFFFFFF
EXPMASK_3    00CDFFFD    

IER    00005003
TSR    0000800F

MEMPROT_L1D (similar for L1P)
MPPA_16    00000080    // bits 7 and 6 are "reserved"
MPPA_17    00000080
MPPA_18    00000080
MPPA_19    00000080
MPPA_20    00000080
MPPA_21    00000080
MPPA_22    00000080
MPPA_23    00000080
MPPA_24    00000080
MPPA_25    00000080
MPPA_26    00000080
MPPA_27    00000080
MPPA_28    00000080
MPPA_29    00000080
MPPA_30    00000080
MPPA_31    00000080

For L2:
...
MPPA_25    0000FFFF
MPPA_26    0000FFFF
MPPA_27    0000FFFF
MPPA_28    00000080
MPPA_29    00000080
MPPA_30    00000080
MPPA_31    00000080


The test was (in the program):

  int *pp = NULL;
  ...

  *pp = 5;
  pp = (int *) 0x009c0005;
  *pp = 5;
  pp = (int *) 0x00f01805;
  *pp = 5;

AET-event (routed to exception) works fine, but the memory protection test doesn't go to the exception (breakpoint at 0x00800000).

(Aha, the event flags DO seem to work (evt 122 and 124), but that's all.)

At breakpoint (just after the shown lines):

EVTFLAG_0    00020008
EVTFLAG_1    00000000
EVTFLAG_2    00000018
EVTFLAG_3    14000000

TS,

You should have access to direct support if you are using this device. Is that not available to you? FYI, the internal product name is provided under NDA and is not used publicly for our protection; the post was edited.

What do you mean by "only upper parts of LiP and L1D exist"? What are your cache settings?

The first *p write appears to write to 0x00000000. Is that correct, or is some code missing for the "..."?

It is good to see that you are getting the event flags set. That means something is working correctly. Have you looked at the fault registers to see what they have captured that led to the event flags being set?

This does say there must be a problem with the NMI setup such that the event combiners do not reach the IFR of the DSP.

Have you looked at the memory at 0x009c0005 and 0x00f01805 to see if 5 was written there or not?

You have exception code at 0x08000000? I would have expected that to be your vector table and the reset vector in particular. Just wanted to confirm that.

Regards,
RandyP

#The first *p write appears to write to 0x00000000. Is that correct, or is some code missing for the "..."?"

Yes, that was used for checking the AET-event. Sorry, I forgot to mention.

"What do you mean by "only upper parts of LiP and L1D exist"? What are your cache settings?"

From the device's manual:

----

...

0184 AE00 - 0184 AE3C(3) - Reserved
0184 AE40 L1DMPPA16 L1D memory protection page attribute register 16
0184 AE44 L1DMPPA17 L1D memory protection page attribute register 17
0184 AE48 L1DMPPA18 L1D memory protection page attribute register 18
0184 AE4C L1DMPPA19 L1D memory protection page attribute register 19
0184 AE50 L1DMPPA20 L1D memory protection page attribute register 20
0184 AE54 L1DMPPA21 L1D memory protection page attribute register 21
0184 AE58 L1DMPPA22 L1D memory protection page attribute register 22

(3) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C64x+
megamaodule. These registers are not supported for the device.

----

"Have you looked at the memory at 0x009c0005 and 0x00f01805 to see if 5 was written there or not?"

No, the data was not written there.

"You have exception code at 0x08000000? I would have expected that to be your vector table and the reset vector in particular. Just wanted to confirm that."

Yes, that's the address for vector 0. Vector 1 is at address 0x08000020

"It is good to see that you are getting the event flags set."

TS,

It has been a while since I was able to get online. Do you have any updates?

Setting a breakpoint at 0x00800000 will only work for a branch to the Reset (Vector 0) vector. The NMI which is used for the Exceptions is on Vector 1 at 0x00800020.

Since the EVTFLAGn bits are being set as expected, the problem you have must be in the path from those EVTFLAGs to the NMI service routine. You must enable several bits and register fields and have your ISR written to handle the NMI.

Have you tried using DSP/BIOS or SYS/BIOS and enabling exceptions within that context? These have been designed and tested already to avoid you having to go through all of this pain. I do not know of a particular example that handles exceptions, but in the BIOS examples for your version there should be one. Please let us know if that is an available option for you, and if so then which version you are using.

Regards,
RandyP