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Hyperlink ECC Error

David Danon
Prodigy 100 points

Hallo.

I have designed a baord based on four pairs of C6678 DSP.

 I running the Hyperlink test provided by TI, two of the DSP pairs are running the test without any errors and in two other DSP pairs I get errors.

Running a loopback test in the failed DSP pairs, pass on one of the DSPs but failed in the other one.

Looking into the status register of the failed DSP show that there are a lot of one ECC error that has been corrected and one double ECC error that can't be corrected and cause the problem.

1. In the status register (HYPERLINK_SERDES_STS) I get an error "Received signal over equalized" for all the laens.

    What is the meaning of this error ? Any idea what could cause to such a error ?

2. Any idea what could cause an Hyperlink internal loopback error ?

 

Thanks.

 David Danon.

 

  • 0
    TI__Expert 4740 points

    Hi,

    all your errror status shows the signal integrity between those two DSP is not good. EQ will work correct if you set it to adaptive operation option. overequalization can be shown by the "bad" input signal. you need to check your connection, cable and all other test environment. you may use your scope to check if the eye diagram pattern is acceptable. Hyperlink is very sensitive about input siganl quality and clock quality. long trace also can cause this kind of trouble. normally less than 6 inch is recommened between DSP.

    Regards,

    Albert  

  • 0 in reply to Albert Bae
    Prodigy 100 points

    Hi.

    Thanks for your response.

    The DSP are connected each other on the same PCB, The trace length of the Hyperlink signal is 3.9 inch.

    My board include 8 DSP arranged as 4 pairs, two of the pairs are working good with the same layout and same signal

    length (we route two DSPs and then copy the routing to the other six DSPs).

    So in terms of signals langth I don't see a problem.

    What about power supply, Is the hyper link interface is sensitive to specific power supply more then the others ?

    Taking in mind that we check 5 board and the behavior is the same, Any other suggestions ?

     

    Thanks.

    David Danon

     

  • 0 in reply to David Danon
    TI__Expert 4740 points

    3.9 inch is fine. you said two pairs are good but other two pairs are bad. what is the main difference between those two pairs? have you checked board design and crosstalk between lanes for the bad pairs? power supply design is very important not only for Hyperlink but also for any other module which has SERDES. I'm not a low level HW engineer, so I can not give you the detail about power but I believe there must be some differerences between those pairs.

    Albert 

  • 0 in reply to Albert Bae
    Prodigy 210 points

    Hi Albert,

    I'm working with David on the design. I would like to emphasize that all the high speed signals (all four SERDES Lanes) are an exact copy for each DSP pairs. This being said plus the fact that for each of the faulty DSP pairs one works in loopback mode without error and the other one fails, may lead to some fault in the power distribution or the clock distribution.

    We would appreciate your opinion on which of the power connections may have more influence over the Hyperlink peripheral.

    Thanks,

    Yishay 

  • 0 in reply to Yishay Hayardeni
    TI__Expert 4740 points

    I don't know why other three pairs of DSPs doesn't work right even though one pair is working right. if you use the same power supply module for all four pairs and the ref clock is same, all your four pairs should work. I'm not that kind of lower HW guy, so I can not tell you the detail. you'd better check your board design is in the boundary of TI recommandation. you need to check TI HW design guide (you can get it from TI external website).

    Sorry if my answer is not helpful.

    Albert  

  • 0 in reply to Albert Bae
    Prodigy 100 points

    I want to add more information:

    1. The same problem happened on 5 different boards.
    2. The problem appears only with two specific DSP pairs.
    3. When we check loopback for each pair, we get problem with the loop back for two specific DSPs (one from each pair) .
    4. The fault DSP is running O.K in loopback test with the lower data rate (3.125G) but fail in the higher rate. But running the regular test (not loopback test) the DSP is fail even with the lower speed.
    5. We try to connect the Hyperlink clock from working DSP to the failed DSP and the result was the same.
    6. We try to run the test with lower MCM frequency input (156.125MHz instead of 312.5MHz) and the result was the same.
    7. There is no layout different between the working DSP and non working DSP in terms of Hyperlink routing. There is different related to the routing of the power supply and the clocks.

    David Danon