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DM8148 VIP Embedded Sync Problem FIQ_STATUS

Terry Neill
Intellectual 600 points

Other Parts Discussed in Thread: TVP5158

Hi folks,

I am currently attempting to configure the DM8148 VIP Port A to receive a 16 bit YUV422 video stream with embedded sync via OMX.

As a test, if I capture using SC_DISCRETESYNC_HSYNC_VSYNC then I can capture complete frames and when I inspect the frames I can see the embedded sync words at the correct points in the frame, so I am reasonably confident that the input to the VIP is correct.

When I switch to embedded sync mode (SC_NON_MUX), no frames are captured.

If I look at the VIP registers in embedded sync mode, I see the following:

0x48105500: 00000001
0x48105504: 2c3c0910
0x48105508: 00000000
0x4810550c: 00000000
0x48105510: 00000000
0x48105514: 00000000
0x48105518: 00000000
0x4810551c: 00030000
0x48105520: ffffffff
0x48105524: ffffffff
0x48105528: ffffffff
0x4810552c: ffffffff
0x48105530: 00000000
0x48105534: 00000000
0x48105538: 00000000
0x4810553c: 00000000
0x48105540: 00000000
0x48105544: 00000000
0x48105548: 00000000

My questions are as follows:

1. What does the value 00030000 mean in the FIQ_STATUS registers?  I cannot find complete documentation about what each of the bit patterns mean.

2. Does the Port A control register look correct in its content? 

3. Are there any other configuration parameters I should be aware of when configuring the VIP for embedded sync?

Any help would be appreciated,

Thanks in advance,

Regards,

Terry

  • 0
    TI__Guru**** 489275 points

    Hi Terry,

     

    This means there is some violation in SAV/EAV codes. Your codes are correct, but the sequence might not be correct, V and H bits may not be toggling correctly, which is why VIP tells its a voilation. Could you check sequence for SAV/EAV codes and also how H and V bits are toggling?

    As such, the configuration is correct, we just need to tell that it is 16 bit embedded sync format..

     

    Regards,

    Brijesh Jadav

  • 0 in reply to Brijesh Jadav
    Intellectual 600 points

    Hi Brijesh,

    Thanks for this answer. I have captured raw frames using discrete HSYNC/VSYNC and the frames and I am analysing the sync word positioning,

    Regards,

    Terry

  • 0 in reply to Brijesh Jadav
    Genius 3180 points

    Hi Brijesh

    I develop on dm8168 using our own design board, using dvrrdk2.80,

    I use tvp5158 capture four pal videos , i find when at room temperature,it works ok,and the register is 

    [m3vpss ] VIP0 : FIQ_STATUS : 0x4810551c = 0x00004400,

    but when the  temperature is minus 40 degrees Celsius， sometimes it will stop video capture, it seems no video capture any more,

    then i check the register is

    [m3vpss ] VIP0 : FIQ_STATUS : 0x4810551c = 0x000044C0,

    it seems FIQ conflict,

    and i also see the status using dvrrdk 3.50, on evm board

    [m3vpss ] VIP0 : FIQ_STATUS : 0x4810551c = 0x00000000,

    So which status is right then ?

    How can i solve the stop capture video problem?

    best regards

    xavier