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EMIF timing registers using m_clk or DDR cycles?

jcm
Prodigy 210 points

Reading the TRM descriptions of the SDRAM_TIM_1 and SDRAM_TIM_2 registers, the timings are specified relative to "number of m_clk cycles", where m_clk is the EMIF functional clock running at half the speed of the DDR PLL.

However when I look at the both the StarterWare and u-boot code, as well as the AM335x DDR register spreadsheet, the timings are calculated relative to tCK, which I read to be the full DDR PLL speed.

Is this an error in the TRM, or have I misunderstood something somewhere?

Thanks,

Jonathan

  • 0
    TI__Guru**** 393215 points
    Hi Jonathan,
     
    Seems to me like a TRM error, because both the AM335x_DDR_register_calc_tool and code are working fine.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 96081 points

    Hi Jonathan

    this is an error in the spreadsheet.  The spreadsheet should be using half of tCK for optimal AC timings.  This was recently brought to my attention and i have not been able to update the spreadsheet on the wiki yet.  uboot and Starterware timings were derived from the spreadsheet.  However, the code still works since they are just programming 2x the timing that is necessary. 

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 210 points

    Hi James,

    Thanks for the reply.

    Do you mean the speadsheet should be using double tCK rather than half?

    Is there a similar confusion with reg_refresh_rate in SDRAM_REG_CTRL. The TRM says it's realtive to m_clk, but the calculation on the wiki uses the DDR rate: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#Setting_Refresh_rate

    If you are updating the spreadsheet, watch out for SDRAM_TIM_3, which is specified relative to DDR not m_clk!

    Regards,

    Jonathan

  • 0 in reply to jcm
    TI__Guru* 96081 points

    Hi Jonathan,

    i did a little more investigation on this, and i think there is an error in the TRM.  The TRM refers to m_clk, which is 1/2 the DDR clock rate, however the original spec of the EMIF module uses "DDR clock cycles" as a measurement in all the SDRAM_TIMx registers.  So i think the original spreadsheet is correct, and I'll have to look into getting the TRM corrected. 

    At any rate, for now it would be safer to use DDR clock cycles for your timing values until i have more time to look into it after the holidays.

    Sorry for all the confusion.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 210 points

    Hi James,

    Thanks for looking into this. It does seem more likely to me that the TRM is wrong than the spreadsheet and existing code, so I'll stick with the tried and tested for the moment.

    Out of curiosity I tried changing the timing values to match the TRM and, to my surprise, it worked with my basic tests on the AM335x Starter Kit:

    SDRAM_REF_CTRL: 0000049d
    SDRAM_TIM_1: 044451c9
    SDRAM_TIM_2: 14193fc9
    SDRAM_TIM_3: 501f830f

    I'm not sure whether that helps! (-:

    Have a good break.

    Jonathan

  • 0 in reply to JJD
    Prodigy 210 points

    Any news on this?

    Jonathan

  • 0 in reply to jcm
    TI__Guru* 96081 points

    Hi Jonathan,

    I confirmed that the error is in the TRM.  The TIM registers should be in terms of DDR clock cycles.  This will be fixed in the next revision. 

    I think it is possible that you could get things working with your experiments, but you would probably see issues under high bandwidth scenarios or with some devices across silicon process distribution.

    Regards,

    James