Other Parts Discussed in Thread: AM3359, AM3358
Hi,
We are designing our own PCB with the AM3359 AZCZ (revision 2.0). We find ourselves having problems in the CPU startup (u-boot.spl)
The board is equipped with DDR3 and 25mhz crystal (with appropriate SYSBOOT[15:14] = 10b.
What we see when the board starts up is that the rom code runs:
-When selecting USB0 as boot device, it will try and BOOTP + TFTP. (but when executing u-boot.spl.bin, somewhere it fails, so we created a stripped down version for GPIO toggling with waitstates)
USB0 seems to have the correct clock settings
-When selecting UART0 as boot device, it will output "^" very fast instead of the expected "C" (as rev 1.0 does @ 115k2 8n1)
we have not analysed if UART0 runs at 115k2 or the data is mangled when traveling from ARM->L3->L4->UART, or this has changed from 1.0 to 2.0, but the data is always the same
-When we strip down the bootloader to toggle a GPIO high/low with timer2 as internval (JTAG -> put it in internal SRAM) we see that a 2000ms interval in reality is 250ms. this interval has been implemented in u-boot mainline using the mdelay() function, which underwater uses timer2.
-CLKOUT1 is running @ 25Mhz (CLKOUT2 has no breakout so not measurable)
-the VDDS_PLLs are 1.762 +- 2mV @ idle
-As a test if the 25Mhz crystal is posing an issue we switched the crystal to 24mhz including SYSBOOT[15:14] 10b on one of our boards and we see the same behavior.
-we are planning to modify one of our boards to run am3359 rev 1.0, to see if the behavior is the same
We are wondering if am335x rev 2.0 has some additional changes that we are unaware of.
Is there a new TRM/spec available for rev 2.0?
How can we verify that the CPU is running as expected?
Is the UART0 "^" output as expected?
All hints are welcome.
The schematics are available upon request (and verified contact), but I cannot post them on the forum.
Kind Regards,
Ron Ytsma.
