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am335x starterkit

Rajas Yaso
Intellectual 280 points

I took a reference design from TMDSSK3358 for my development board.I prefer that i am using the same DDR3 ram as SK kit but  In that schematic design of MT41J128M16JT-125 (ddr3) has a ball name - A14 ( Ball number T7)  connected to am335x processor DDR_A14 (Ball number H4),

In the DDR3 ram Datasheet,that A14th ball T7 denoted as NC (No Connection).How it works?? Totally 6 NC pins including T7................

Clarify me...

  • 0
    TI__Guru 64500 points

    The AM335x starter kit, TMDSSK3358, was designed with the potential to accomodate a larger density DRAM device which may necessitate using the A14 address line.  Therefore, that signal is routed.  There should not be an issue with this signal routed.

  • 0 in reply to BrandonAzbell
    Intellectual 280 points

    In DDR3 ram Datasheet, T7 ball is denoted as NC (not connected).The ball has no connection with DDR3 RAM and left floating.Then we populated with A15 address line.

    I understand your words...It's not an issue,but How does it works??? How does it communicates???

  • 0
    Intellectual 270 points

    Hi,

    Can really the AM335x address 256Mx16 (512MB) DDR3 devices? I've been reading some old threads and is not clear at all. Just in case I just add A14.

    Regarding also to the schematic of the starter kit:

    1. Are CKE and RESETn pull resistors mandatory?

    2. Why CKE is not VTT terminated?

    I'm ending routing the memory for a custom board and this info would be appreciated.

    Thanks.

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Hi Manuel,
     
    1. Are CKE and RESETn pull resistors are not mandatory, but it's good to have them. CKE pulldown allows DDR self-refresh when processor is in low-power mode. RESETn pullup is for the same reason - to prevent the signal from floating.
     
    2. CKE should be VTT terminated. RESETn doesn't need termination.
     
    Adding the extra address lines will not interfere with board functionality. It will just help if you need to expand the memory at a later point.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Thanks Biser,

    Great!: I will add the 2 pull resistors, and replace RESET by CKE in the termination resistor pack what gets me just 24 termination resistors (3 packs of 8). Also I will modify the footprint for 14x10mm package to be ready to mount 512MB chips.

    Please only one more question about DDR3. I've read this post about why you are "scrambled" the data nets:

    http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/791/t/233481.aspx

    Where is the software patch to get the original addressing? I already have routed with normal relationship (DDR_Dx to DQx) and I would prefer to don't modify the design.

    Thanks.

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Hi Manuel,
     
    The data nets are not really "scrambled". The post you refer to comments that data bits within a data lane can be swapped, but only on the memory side. For example:
     
    Normal connection is like this:
     
    AM335X D0 - DDR D0
    AM335X D1 - DDR D1
    .......................................
    AM335X D7 - DDR D7
     
    But this is also allowed (any variation on memory side is OK):
     
    AM335X D0 - DDR D3
    AM335X D1 - DDR D6
    .......................................
    AM335X D7 - DDR D1
     
    Of course, associated data control signals must always be connected properly:
     
    DQS0, DQS0n and DQM0 must go with D0-D7
    DQS1, DQS1n and DQM1 must go with D8-D15
     
    The bit swapping within a data lane is used to facilitate routing, if necessary. This has no relation to software at all, nor are any software changes necessary.
     
     
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Biser,

    Now I understand it: really interesting and simple.

    Thanks!