C66 uart interrupt problem?

li dong

hi,

I have a problem about c6678 interrupt setup using sys/bios. my code is below, i do not know why it cann't work.

irq = Hwi_disable();

PRT("1\n");
/* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
CpIntc_dispatchPlug(CSL_INTC0_UARTINT, (CpIntc_FuncPtr)UartReceiveIsr, 0, TRUE);
PRT("2\n");
/* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
CpIntc_mapSysIntToHostInt(0, CSL_INTC0_UARTINT, 8);

/* Enable the Host Interrupt. */
CpIntc_enableHostInt(0, 8);

/* Enable the System Interrupt */
CpIntc_enableSysInt(0, CSL_INTC0_UARTINT);

/* Get the event id associated with the host interrupt. */
eventId = CpIntc_getEventId(8);

/* Plug the CPINTC Dispatcher. */
EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, 8, TRUE);

CpIntc_enableAllHostInts(0);
PRT("eventId %d , CSL_INTC0_UARTINT %d,3\n",eventId, CSL_INTC0_UARTINT);
Hwi_restore(irq);

void UartInit(void)
{
memset(print_buffer, 0x0, sizeof(print_buffer));

/* Allows access to the divisor latches of the baud generator during a */
/* read or write operation (DLL and DLH) */
CSL_FINS(hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_ENABLE);
/* Break condition is disabled. */
CSL_FINS(hUartRegs->LCR, UART_LCR_BC, CSL_UART_LCR_BC_DISABLE);
/* Stick parity is disabled. */
CSL_FINS(hUartRegs->LCR, UART_LCR_SP, CSL_UART_LCR_SP_DISABLE);
/* Odd parity is selected */
CSL_FINS(hUartRegs->LCR, UART_LCR_EPS, CSL_UART_LCR_EPS_ODD);
/* No PARITY bit is transmitted or checked */
CSL_FINS(hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_DISABLE);

/* Set the baudrate,for accessing LCR[7] should be enable */
hUartRegs->DLL = DLL_VAL;
hUartRegs->DLH = DLM_VAL;

/* Allows access to the receiver buffer register (RBR), */
/* the transmitter holding register (THR), and the */
/* interrupt enable register (IER) selected. */
CSL_FINS(hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_DISABLE);
/* Even Parity is selected */
CSL_FINS(hUartRegs->LCR, UART_LCR_EPS, CSL_UART_LCR_EPS_EVEN);
/* Parity Enable */
CSL_FINS(hUartRegs->LCR, UART_LCR_PEN, CSL_UART_LCR_PEN_ENABLE);

/* Disable THR, RHR, Receiver line status interrupts */
CSL_FINS(hUartRegs->IER, UART_IER_ERBI, 1);
CSL_FINS(hUartRegs->IER, UART_IER_ETBEI, 1);
CSL_FINS(hUartRegs->IER, UART_IER_ELSI, 1);
CSL_FINS(hUartRegs->IER, UART_IER_EDSSI, 1);

/* If autoflow control is desired,
* write appropriate values to the modem
* control register (MCR). Note that all UARTs
* do not support autoflow control, see
* the device-specific data manual for supported features.
*
* MCR
* ====================================================
* Bit Field Value Description
* 5 AFE 0 Autoflow control is disabled
* 4 LOOP 0 Loop back mode is disabled.
* 1 RTS 0 RTS control (UARTn_RTS is disabled,
* UARTn_CTS is only enabled.)
* =====================================================
*
*
*/

hUartRegs->MCR = 0;

/* Choose the desired response to
* emulation suspend events by configuring
* the FREE bit and enable the UART by setting
* the UTRST and URRST bits in the power and
* emulation management register (PWREMU_MGMT).
*
*
* PWREMU_MGMT
* =================================================
* Bit Field Value Description
* 14 UTRST 1 Transmitter is enabled
* 13 URRST 1 Receiver is enabled
* 0 FREE 1 Free-running mode is enabled
* ===================================================
*
*/
hUartRegs->PWREMU_MGMT = 0x6001;

/* Cleanup previous data (rx trigger is also set to 0)*/
/* Set FCR = 0x07; */
CSL_FINS(hUartRegs->FCR, UART_FCR_FIFOEN, CSL_UART_FCR_FIFOEN_ENABLE);
CSL_FINS(hUartRegs->FCR, UART_FCR_TXCLR, CSL_UART_FCR_TXCLR_CLR);
CSL_FINS(hUartRegs->FCR, UART_FCR_RXCLR, CSL_UART_FCR_RXCLR_CLR);
CSL_FINS(hUartRegs->FCR, UART_FCR_DMAMODE1, CSL_UART_FCR_DMAMODE1_DISABLE);
CSL_FINS(hUartRegs->FCR, UART_FCR_RXFIFTL, CSL_UART_FCR_RXFIFTL_CHAR1);

return;
}

over 12 years ago

0 HRi over 12 years ago

Guru 10750 points

Hi Li Dong,

Please check the below example which is in the DSP_BIOs documentation,

An example of using CpIntc during runtime to plug the ISR handler for System interrupt 15 mapped to Host interrupt 8 on Hwi 7.

  Int eventId;
  Hwi_Params params;
  Error_Block eb;

  // Initialize the error block
  Error_init(&eb);

  // Map system interrupt 15 to host interrupt 8 on Intc 0
  CpIntc_mapSysIntToHostInt(0, 15, 8);

  // Plug the function and argument for System interrupt 15 then enable it
  CpIntc_dispatchPlug(15, &myEvent15Fxn, 15, TRUE);

  // Enable Host interrupt 8 on Intc 0
  CpIntc_enableHostInt(0, 8);

  // Get the eventId associated with Host interrupt 8
  eventId = CpIntc_getEventId(8);
   
  // Initialize the Hwi parameters
  Hwi_Params_init(&params);

  // Set the eventId associated with the Host Interrupt
  params.eventId = eventId;

  // The arg must be set to the Host interrupt
  params.arg = 8;

  // Enable the interrupt vector
  params.enableInt = TRUE;

  // Create the Hwi on interrupt 7 then specify 'CpIntc_dispatch'
  // as the function.
  Hwi_create(7, &CpIntc_dispatch, &params, &eb);

Thanks,

HR

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C66 uart interrupt problem?