Can not write the ARM L2 Cache Auxiliary Control Register

Y tck

Hi,

I want to enable the ECC of L2 Cache.I can not write the value to the L2 Cache Auxiliary Control Register ,additional,I just write the value what I read from the L2 Cache Auxiliary Control Register ,the processor also goes into an instruction exception .

MRC p15, #1, r1, c9, c0, #2 ;Read L2 Cache Auxiliary Control Register

MCR p15, #1, r1, c9, c0, #2 ;Write L2 Cache Auxiliary Control Register

What's wrong ?

Thanks.

YanTCK

over 12 years ago

0 Y tck over 12 years ago

Intellectual 835 points

Before access the L2 CACR,the Processor must be a secure state,and it must in Monitor mode so that can change the state secure or Nonsecure ,but I do not kown how to "Monitor mode " .

0 Steve Kipisz over 12 years ago in reply to Y tck

TI__Genius 15510 points

Take a look in the ARM MPU Subsystem chapter in the TRM. I have Rev G. of the TRM and section 3.1.4.2.2 describes the SMC instructions to access CP15 registers in Monitor mode.

Steve K.

Processors

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Can not write the ARM L2 Cache Auxiliary Control Register