Hi all,
In OMAP35x TO AM37x Hardware Migration Guide (http://processors.wiki.ti.com/index.php/OMAP35x_To_AM37x_Hardware_Migration_Guide), it is mentioned that Display sub system data lines need to be muxed to SYSBOOT pins for operating AM37x in two modes (PCLK <60 MHz & PCLK >60 MHz).
It is mentioned as "Backward compatibility is maintained if your pixel clock on DSS interface is <= 60 MHz. But if your pixel clock is higher, 60< PCLK <= 75 MHz, you would need to use the High Speed Mode pinmux scheme. For all new AM37x designs, High Speed Mode pinmux scheme should be used. "
In our new design, we are making use of both small size LCD and HDMI moniter for display.
LCD pclk - less than 60 MHz
HDMI pclk - greater than 60 MHz
I have designed in schematics with both LCD & HDMI transceiver data lines configured in high speed mode pinmux scheme. Is that okay?
i.e d0-d5 (display side) --> d18-d23 (omap side)
d6-d17(display side)--> d6-d17 (omap side)
d18-d23(display side)-->sysboot(0,1,3,4,5,6)
Since I am not sure that LCD with pixel clock less than 60 MHz work in high speed mode pinmux scheme.
Thanks,
Karthik
