OMAP-L138 VTP IO Buffer Calibration does not succeed

Have you also looked at the following threads?

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/p/141775/521649.aspx#521649

There is a mention of issues with LOCK bit and TRST configuration etc.

Hi Paul,

I looked those threads, and I'm quite sure I'm clearing the lock bit and that TRST is okay. I ran the OMAP_L1x_debug.gel script referenced in one of the threads. Could you help me with the output? I'm not sure which registers the DEV_INFO_xx values are referring to. Maybe there's a clue in here:

C674X_0: GEL Output:
---------------------------------------------
C674X_0: GEL Output: |             Device Information            |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x0000001E
C674X_0: GEL Output: DEV_INFO_03 = 0x00000033
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x08080080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6813653-2-30-23
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 3,0,0,10960
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3830306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x0201701E
C674X_0: GEL Output: DEV_INFO_25 = 0x0067F7D5
C674X_0: GEL Output: DEV_INFO_06 = 0x08080080
C674X_0: GEL Output: DEV_INFO_26 = 0x55A00003
C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |               BOOTROM Info                |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k008
C674X_0: GEL Output: Silicon Revision 2.1
C674X_0: GEL Output: Boot pins: 30
C674X_0: GEL Output: Boot Mode: Emulation Debug
C674X_0: GEL Output:
ROM Status Code: 0x00000001
Description:C674X_0: GEL Output: DSP was put to sleep
C674X_0: GEL Output:
Program Counter (PC) = 0x1181135A
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              Clock Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize 1.2V square wave input.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE:  All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 24 MHz.  If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 100 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 100 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 50 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 300 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 300 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 300 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:    EDMA3CC (0)        STATE = 3
C674X_0: GEL Output: Module 1:    EDMA3 TC0          STATE = 3
C674X_0: GEL Output: Module 2:    EDMA3 TC1          STATE = 0
C674X_0: GEL Output: Module 3:    EMIFA (BR7)        STATE = 0
C674X_0: GEL Output: Module 4:    SPI 0              STATE = 0
C674X_0: GEL Output: Module 5:    MMC/SD 0           STATE = 0
C674X_0: GEL Output: Module 6:    AINTC              STATE = 3
C674X_0: GEL Output: Module 7:    ARM RAM/ROM        STATE = 3
C674X_0: GEL Output: Module 9:    UART 0             STATE = 0
C674X_0: GEL Output: Module 10:    SCR 0 (BR0/1/2/8)  STATE = 3
C674X_0: GEL Output: Module 11:    SCR 1 (BR4)        STATE = 3
C674X_0: GEL Output: Module 12:    SCR 2 (BR3/5/6)    STATE = 3
C674X_0: GEL Output: Module 13:    PRUSS              STATE = 0
C674X_0: GEL Output: Module 14:    ARM                STATE = 3
C674X_0: GEL Output: Module 15:    DSP                STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:    EDMA3CC (1)        STATE = 0
C674X_0: GEL Output: Module 1:    USB0 (2.0)         STATE = 0
C674X_0: GEL Output: Module 2:    USB1 (1.1)         STATE = 0
C674X_0: GEL Output: Module 3:    GPIO               STATE = 0
C674X_0: GEL Output: Module 4:    UHPI               STATE = 0
C674X_0: GEL Output: Module 5:    EMAC               STATE = 0
C674X_0: GEL Output: Module 6:    DDR2 and SCR F3    STATE = 3
C674X_0: GEL Output: Module 7:    MCASP0 + FIFO      STATE = 0
C674X_0: GEL Output: Module 8:    SATA               STATE = 0
C674X_0: GEL Output: Module 9:    VPIF               STATE = 0
C674X_0: GEL Output: Module 10:    SPI 1              STATE = 0
C674X_0: GEL Output: Module 11:    I2C 1              STATE = 0
C674X_0: GEL Output: Module 12:    UART 1             STATE = 0
C674X_0: GEL Output: Module 13:    UART 2             STATE = 0
C674X_0: GEL Output: Module 14:    MCBSP0 + FIFO      STATE = 0
C674X_0: GEL Output: Module 15:    MCBSP1 + FIFO      STATE = 0
C674X_0: GEL Output: Module 16:    LCDC               STATE = 0
C674X_0: GEL Output: Module 17:    eHRPWM (all)       STATE = 0
C674X_0: GEL Output: Module 18:    MMC/SD 1           STATE = 0
C674X_0: GEL Output: Module 19:    UPP                STATE = 0
C674X_0: GEL Output: Module 20:    eCAP (all)         STATE = 0
C674X_0: GEL Output: Module 21:    EDMA3 TC2          STATE = 0
C674X_0: GEL Output: Module 24:    SCR-F0 Br-F0       STATE = 3
C674X_0: GEL Output: Module 25:    SCR-F1 Br-F1       STATE = 3
C674X_0: GEL Output: Module 26:    SCR-F2 Br-F2       STATE = 3
C674X_0: GEL Output: Module 27:    SCR-F6 Br-F3       STATE = 3
C674X_0: GEL Output: Module 28:    SCR-F7 Br-F4       STATE = 3
C674X_0: GEL Output: Module 29:    SCR-F8 Br-F5       STATE = 3
C674X_0: GEL Output: Module 30:    Br-F7 (DDR Contr)  STATE = 3
C674X_0: GEL Output: Module 31:    L3 RAM, SCR-F4, Br-F6 STATE = 3

Hey Sam,

So the GEL file works on the EVM but not your board?  This would lead me to believe it's probably a hardware issue.  Have you already tried comparing the schematics and find any related differences? 

If you want, you can give us the schematic/capture and maybe we can take a look.  You can either throw them up here (public), send me a message, or send them through Paul.

Thanks,

JD

Hi JD,

Yes, I suspect a hardware problem as well. I've already sent the schematic through Paul with the caveat that two of the OMAP pins (DDR_ZP and DDR_VREF) are connected incorrectly on the schematic, but have been fixed by modding our boards. I'm interested to know what exactly could cause the VTP IO calibration to fail, assuming that the DDR_ZP and DDR_VREF pins are connected correctly. Any guidance here would help us know where to look for a solution.

Thanks,
Sam

Hey Sam,

I recieved your schematic from Paul.  I'm going to compare the mDDR connections to the reference in out datasheet, but at a quick look it seems alright. 

I'm not exactly sure how the VTP IO Buffer Calibration works, but I do know that it is dynamically truning the IO output impedance to match that of the PCB.  I can see how variations in impedance on the PCB could cause issues that could keep VTP from calibrating.  The follow documents discuss recommended layout and PCB procedures for the mDDR interface.  Please review your layout with these guidelines. 

Datasheet section 5.11 (pg. 126-139).  

TI’s PCB Routing Rule-Based DDR Timing Specification.

I'll let you know if I see any issues in the schematic.

Thanks,

JD

Hey Sam,

I reviewed the schematic compared to our datasheet and haven't found any issues other than those that you mentioned have been already fixed. 

Have you had a chance to review the guidelines above?  Are there any notable difference from your current layout?

Thanks,

JD   

There have been cases where hardware issues, soldering issues, layout issues have caused VTP calibration fails.

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/141775.aspx

I am assuming multiple boards are behaving this way? I see that you are using emulation boot mode. Can you see if your board will boot up via whatever boot mechanism you have on your board? The ROM code also has the VTP calibration function and you could see if configuring ddr during boot works or not (chances are low if your board has issues).

Regards

Mukul

Hi JD,

Yes, we've reviewed the layout guidelines, and we have found some violations that we will fix in a board spin along with the mistakes already mentioned. From what Mukul said, and what I was already beginning to believe, it looks like our hand-wired fixes may not work due to impedance issues so the board spin may get us there. We'll let you know if that works.

Thanks,

Sam