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Problem with L2 Cache (Coherence Problem)

Ahmed Zaki
Prodigy 110 points

Other Parts Discussed in Thread: OMAPL138, SYSBIOS

My target is an OMAPL138

Tools:

CCS version = 5.3.0.00090

TI compiler = 7.4.1

SYSBIOS = 6.34.4.22

XDCtools = 3.24.5.48

edma3lld = 2.11.6

I use MCASP to get audio in to the DSP. I make edma to cpy data from the MCASP peripheral to memory.

I want to use L1 & L2 as Cache. I put my code & Data & stack in DDR.

The destination address I save data from MCASP into two global array. 

When I use L1 only and do not use L2. & make Cache_inv for the receive buffers , Cache_wb for the transmit buffer. It works correctly.

But when I use L1 and use L2 as cache & make Cache_inv & Cache_wb. It doesn't work correct. so there is a problem with L2 in caching data.

Could you help me?

Thanks,
Best Regards,
Ahmed Zaki