need breakpoint while debug to let program goes smoothly in 6678

Zhao Shui

Hi,everyone

When I debug my program I find it stuck in somewhere,so I set a breakpoint near the end of my code and start to debug again,then the arrow stop exactly where my breakpoint is set,and then I resume my program and it ends normally by printing some message.

So it seems I need a breakpoint to let it run smoothly,quite strange to me.

I believe there must be something wrong with my code,and I guess too much cache writeback in my code may cause problem.so I paste some relative code here:

*(int*)rxflag_add=0;

Cache_wb((Ptr) rxflag_add, sizeof(int), Cache_Type_ALL, TRUE);

Trans_sim();

txflag=1;

Cache_wb((Ptr) &txflag, sizeof(txflag), Cache_Type_ALL, TRUE);

（set breakpoint here）txend=1;

Cache_wb((Ptr) &txend, sizeof(txend), Cache_Type_ALL, TRUE);

when I debug without a breakpoint, I find txend is still 0 when it runs to the end,while with a breakpoint and resuming txend is set to 1.

I can not figure why this is happening,could anyone help me?

Thank you for your patience.

Zhao

over 12 years ago

0 HRi over 12 years ago

Guru 10750 points

Hi Zhao,

Are you using HW or SW breakpoint? if you are using SW than use HW and see if it's the same,

Thanks,

0 Zhao Shui over 12 years ago in reply to HRi

Intellectual 910 points

Hi,HR

Thank you for your patience,I believe I use the SW breakpoint because I only add it when I debug by double clicking.And could you please show me how to add a HW in my code(I'm new with this actually)?Do I have to use the sys/bios HWI? or something else.

Thank you very much.☺

Best Regards

Zhao

0 HRi over 12 years ago in reply to Zhao Shui

Guru 10750 points

Hi Zhao,

For setting HW breakpoint when you are on the line you want to break click the mouse right button and select breakpoint -> HW breakpoint,

Thanks,

Haim

0 RandyP over 12 years ago in reply to HRi

TI__Guru* 84110 points

Zhao,

Each Cache_wb will write in groups determined by the CACHE_LINE_SIZE and aligned to CACHE_LINE_SIZE, so doing this command for a single variable will also write other variables to the external memory.

To determine if your problem is with cache coherency, move these variables to L2 SRAM and try again. If they are on the stack, then try moving the stack to L2 SRAM.

Try putting a delay or a FENCE (see the CPU & Instruction Set Guide) after the write to txend.

How are you observing the value of txend at the end to determine that it is 0 or 1?

Why are you doing so many Cache_wb commands? Are you interacting with peripherals or other bus masters or other CorePacs?

Where in memory are the variables located that you show in your code above?

What do you mean by "some relative code"? Is there a lot going on in between some of these lines of code?

Does Trans_sim() have any direct relationship to these variables?

Regards,
RandyP

0 Zhao Shui over 12 years ago in reply to RandyP

Intellectual 910 points

Hi,RandyP

I'm sorry to forget giving more details.

1.I put my data in MSMC,core0 and core1 communicate by reading the same variable stored in MSMC,that's why there are so many cache wb in my code.txend is a flag given by core0 to tell core1:the transfer ends.

2.I observe txend by memory browzer.

3.All my variables are stored in MSMC.In rtsc platform file,core0 has half MSMC and core1 has the other.

4.I've uploaded my code both the trans(core0) and recv(core1).It is used to simulate a "block ACK",namely core0 "transfer" data to core1 and core1 tells core0 whether the data is right.ACK is generated by CRC16.

5.Trans_sim() is used to copy data from core0 to core1,but both their data are stored in MSMC,so it actually is a data copy from MSMC to MSMC,in my code this is completed by EDMA3.

I hope this will help.Thank you very much.

Best Regards

Zhao

Fullscreen 8103.trans.c Download

#include<std.h>
#include<string.h>
#include<stdio.h>
#include<stddef.h>
#include<global.h>
#include<ti/sysbios/family/c66/Cache.h>
#include<edma3_common.h>
#include<edma3_drv.h>
#include<ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>

/* OPT Field specific defines */
#define OPT_SYNCDIM_SHIFT                   (0x00000002u)
#define OPT_TCC_MASK                        (0x0003F000u)
#define OPT_TCC_SHIFT                       (0x0000000Cu)
#define OPT_ITCINTEN_SHIFT                  (0x00000015u)
#define OPT_TCINTEN_SHIFT                   (0x00000014u)

#define Rx_block_add 0x0c201410
#define rxflag_add 0x0c20697c
#define rxini_add 0x0c206978

int data_push;//ָ��data_pool����һ��Ҫ���뷢�ͷ�block������֡

int data_push_num;//��¼��һ��Ҫ���뷢�ͷ�block������֡�ĸ���

Uint8 data_pool[data_frame_num][data_frame_size];//�洢���д���������֡

struct block Tx_block[block_size];//���ͷ���block

int retrans_num[block_size];//���ͷ�block�ش�������¼��

Uint16 Tx_ack;//ACK֡

int txini;//���ͷ���ɳ�ʼ��flag

int txflag;//���ͷ������������flag

int txend;//���ͷ�����������ݴ���

EDMA3_DRV_Handle hEdma;

unsigned int chId=0;

unsigned int tcc=0;

EDMA3_DRV_Result result=EDMA3_DRV_SOK;

Uint16 GetCrc16(Uint8 *ptr, Uint16 len);//����crc���ɺ���

/*��ʼ��EDMA3����*/
void EDMA3_Initialize(){

	EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};

	hEdma=edma3init(0,&result);

	if (result == EDMA3_DRV_SOK){
		result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc,(EDMA3_RM_EventQueue)0,NULL, NULL);
	}

	if (result == EDMA3_DRV_SOK){
		/* Fill the PaRAM Set with transfer specific information */
		paramSet.srcAddr    = (unsigned int)(&Tx_block);
		paramSet.destAddr   = (unsigned int)(Rx_block_add);
		paramSet.srcBIdx    = sizeof(Tx_block[0]);
		paramSet.destBIdx   = sizeof(Tx_block[0]);
		paramSet.srcCIdx    = 0;
		paramSet.destCIdx   = 0;
		paramSet.aCnt       = sizeof(Tx_block[0]);
		paramSet.bCnt       = block_size;
		paramSet.cCnt       = 1;
		paramSet.bCntReload = 0;
		/* Link function is shut down */
		paramSet.linkAddr   = 0xFFFFu;
		/* Src & Dest are in INCR modes */
		paramSet.opt &= 0xFFFFFFFCu;
		/* Program the TCC */
		paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);
		/* Disable Intermediate & Final transfer completion interrupt */
		paramSet.opt |= (0 << OPT_ITCINTEN_SHIFT);
		paramSet.opt |= (0 << OPT_TCINTEN_SHIFT);
		/* AB Sync Transfer Mode */
		paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);;

		/*write the PaRAM Set. */
		result = EDMA3_DRV_setPaRAM(hEdma, chId, &paramSet);
	}

	if (result == EDMA3_DRV_SOK){
	    result = EDMA3_DRV_linkChannel (hEdma, chId, chId);
	}
}

/*��ʼ�����д洢��Ԫ�Լ�ȫ�ֱ���*/
void Initialize(){
	int i,j;

	txini=0;//���ͷ���ʼ��δ���
	Cache_wb((Ptr) &txini, sizeof(txini), Cache_Type_ALL, TRUE);

	EDMA3_Initialize();

	for(i=0;i<data_frame_num;i++){//����֡��ʼ����ÿһ֡�ĵ�һ�ֽ����ڼ�¼������֡����ţ�0~255
		data_pool[i][0]=i;
		for(j=1;j<data_frame_size;j++){
			data_pool[i][j]=j;
		}
	}

	for(i=0;i<block_size;i++){//���ͷ�block��ʼ��
		memcpy(&Tx_block[i].data,data_pool[i],sizeof(Tx_block[i].data));
		Tx_block[i].crc=0;
	}
	Cache_wb((Ptr) &Tx_block, sizeof(Tx_block), Cache_Type_ALL, TRUE);

	for(i=0;i<block_size;i++){//���ͷ�block�ش�������¼���ʼ��
		retrans_num[i]=0;
	}

	Tx_ack=ack_initial;//���ͷ�ACK��ʼ��
	data_push_num=0;//ȫ�ֱ�����ʼ��
	data_push=0;//ȫ�ֱ�����ʼ��

    txend=0;//���ͷ�δ����������ݷ���
    Cache_wb((Ptr) &txend, sizeof(txend), Cache_Type_ALL, TRUE);

	txflag=0;//���ͷ�δ������ݷ���
    Cache_wb((Ptr) &txflag, sizeof(txflag), Cache_Type_ALL, TRUE);

    txini=1;//���ͷ���ʼ�����
    Cache_wb((Ptr) &txini, sizeof(txini), Cache_Type_ALL, TRUE);
}

/*���ͷ����ݵ�ǰ�յ���ACK֡������һ��Ҫ���������֡*/
void ACK_process(){
	int i;
	int Tx_block_p=0;//��¼���ͷ�block����һ���ش�֡�ƶ�����λ��

	Cache_inv((Ptr) &Tx_ack, sizeof(int), Cache_Type_ALL, TRUE);
	for(i=0;i<block_size;i++){
		if((Tx_ack&(compare>>i))==0){//��ACK��ӦλΪ0������Ӧ����֡δ����ȷ����
			retrans_num[i]++;//��������֡�ش�������1
			if(retrans_num[i]>max_retrans_num){//���ش������Ѿ�������������ش����������Ѿ��ɹ����䴦��
				data_push_num++;
		    }
			else{//���򽫸�����֡������Tx_block_p��ָλ��
				if(i!=Tx_block_p){
					Tx_block[Tx_block_p]=Tx_block[i];
					retrans_num[Tx_block_p]=retrans_num[i];
				}
				Tx_block_p++;
			}
		}
	    else
	    	data_push_num++;//�ѳɹ����������֡�Ƴ����ͷ�block������һ�����뷢�ͷ�block������֡������1
    }
}

/*����ACK_process()�Ĵ�����������µķ��ͷ�block*/
void Push_block(){
	int i;

	for(i=0;i<data_push_num;i++){
		if(data_push<data_frame_num){//��data_pool����������Tx_block
			memcpy(&Tx_block[block_size-data_push_num+i].data,data_pool[data_push],sizeof(Tx_block[block_size-data_push_num+i].data));
			Tx_block[block_size-data_push_num+i].crc=GetCrc16(&(Tx_block[block_size-data_push_num+i].data[0]), sizeof(Tx_block[block_size-data_push_num+i].data));
			retrans_num[block_size-data_push_num+i]=0;
		}
        data_push++;
	}
	Cache_wb((Ptr) &Tx_block, sizeof(Tx_block), Cache_Type_ALL, TRUE);
	data_push_num=0;
}

/*ģ������֡���ŵ��Ĵ������*/
void Trans_sim(){
    result = EDMA3_DRV_enableTransfer (hEdma,chId,EDMA3_DRV_TRIG_MODE_MANUAL);
}

/*��data_pool��ʣ�����ݲ������������blockʱ,��ɷ��ͷ�block��ʣ�����ݵĴ���,������֮ǰ����*/
void Final_trans(){
	int i;
	int final_block_size=block_size-(data_push-data_frame_num);
	Uint16 final_ack=0;//��¼���һ��Tx_block�����ݵĴ������
    Uint16 final=0;

	for(i=0;i<final_block_size;i++){
		final+=(compare>>i);
	}

	Cache_inv((Ptr) &Tx_ack, sizeof(int), Cache_Type_ALL, TRUE);
    final_ack=Tx_ack;

	while((final_ack&final)!=final){
		Cache_inv((Ptr) rxflag_add, sizeof(int), Cache_Type_ALL, TRUE);
		if(*(int*)rxflag_add==1){
			for(i=0;i<final_block_size;i++){
				if((Tx_ack&(compare>>i))!=0)
					final_ack|=(compare>>i);
				else{
					retrans_num[i]++;
					if(retrans_num[i]>max_retrans_num){
						final_ack|=(compare>>i);
					}
				}
			}

			*(int*)rxflag_add=0;
			Cache_wb((Ptr) rxflag_add, sizeof(int), Cache_Type_ALL, TRUE);

			Trans_sim();

			txflag=1;//���ͷ������������
			Cache_wb((Ptr) &txflag, sizeof(txflag), Cache_Type_ALL, TRUE);
		}
	}
}

void main(){
	Initialize();//��ɳ�ʼ��

	Cache_inv((Ptr) rxini_add, sizeof(int), Cache_Type_ALL, TRUE);
	while(*(int*)rxini_add!=1){//�ȴ����շ���ʼ�����
		Cache_inv((Ptr) rxini_add, sizeof(int), Cache_Type_ALL, TRUE);
	}

	while(data_push<data_frame_num){
		Cache_inv((Ptr) rxflag_add, sizeof(int), Cache_Type_ALL, TRUE);
		if(*(int*)rxflag_add==1){//�ȴ����շ�ack�������
			ACK_process();

            *(int*)rxflag_add=0;
            Cache_wb((Ptr) rxflag_add, sizeof(int), Cache_Type_ALL, TRUE);

			Push_block();//����µ�Tx_block
			Trans_sim();//ģ�����ݴ������

			txflag=1;//���ͷ����ݴ������
			Cache_wb((Ptr) &txflag, sizeof(txflag), Cache_Type_ALL, TRUE);
		}
	}
    Final_trans();//������һ��Tx_block�ڵ����ݴ���

    txend=1;//���ͷ�����������ݷ���
    Cache_wb((Ptr) &txend, sizeof(txend), Cache_Type_ALL, TRUE);
}

Fullscreen 4135.recv.c Download

#include<std.h>
#include<string.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<global.h>
#include<ti/sysbios/family/c66/Cache.h>

#define Tx_ack_add 0x0c02d240
#define txflag_add 0x0c02d248
#define txini_add 0x0c02d244
#define txend_add 0x0c02d24c

struct block Rx_block[block_size];//���շ���block

Uint16 Rx_ack;//ACK֡

int Rx_record[data_frame_num];//���շ����ڼ�¼���յ�����֡�ļ�¼��

int rxini;//���շ���ɳ�ʼ��flag

int rxflag;//���շ�����ack���flag

Uint16 IsCrc16Correct(Uint8 *pData, Uint16 len);//����crcУ�麯��

/*��ʼ�����д洢��Ԫ�Լ�ȫ�ֱ���*/
void Initialize(){
	int i,j;

	rxini=0;//���շ���ʼ��δ���
	Cache_wb((Ptr) &rxini, sizeof(rxini), Cache_Type_ALL, TRUE);

	for(i=0;i<block_size;i++){//���շ�block��ʼ��
		for(j=0;j<data_frame_size;j++){
			Rx_block[i].data[j]=0;
			Rx_block[i].crc=0;
		}
	}

    rxflag=1;//���շ�ack����δ���
    Cache_wb((Ptr) &rxflag, sizeof(rxflag), Cache_Type_ALL, TRUE);

    rxini=1;//���շ���ʼ�����
    Cache_wb((Ptr) &rxini, sizeof(rxini), Cache_Type_ALL, TRUE);
}

/*ģ������֡���ŵ��Ĵ������*/
void Trans_sim(){
	int interfere;
	Cache_inv((Ptr) &Rx_block, sizeof(Rx_block), Cache_Type_ALL, TRUE);
	srand((unsigned)time(NULL));//������������������ģ�⣬�˴�Ϊÿһ��block��3������֡��������
    interfere=(rand()%block_size);
    Rx_block[interfere].data[1]=2;
    Rx_block[(interfere+2)%block_size].data[1]=2;
    Rx_block[(interfere+4)%block_size].data[1]=2;
}

/*���շ�У��crc������ACK֡������¼����ȷ��������֡�����*/
void ACK_submit(){
	int i;
	Uint16 correct;
	Rx_ack=0;

    for(i=0;i<block_size;i++){
    	correct=IsCrc16Correct(&(Rx_block[i].data[0]), sizeof(Rx_block[i]));
    	if(correct==1)
    		Rx_record[Rx_block[i].data[0]]=1;//��¼����ȷ��������֡�����
        Rx_ack+=(correct<<(block_size-1-i));//��crcУ��������ACK֡
	}
    Cache_wb((Ptr) &Rx_ack, sizeof(Rx_ack), Cache_Type_ALL, TRUE);
    memcpy((Uint16*)Tx_ack_add,&Rx_ack,sizeof(Rx_ack));//����ack
    Cache_wb((Ptr) Tx_ack_add, sizeof(Rx_ack), Cache_Type_ALL, TRUE);
}

void main(){
	int i;
	int num=0;

	Initialize();//��ɳ�ʼ��

	Cache_inv((Ptr) txini_add, sizeof(int), Cache_Type_ALL, TRUE);
	while(*(int*)txini_add!=1){//�ȴ����ͷ���ʼ�����
		Cache_inv((Ptr) txini_add, sizeof(int), Cache_Type_ALL, TRUE);
	}

	Cache_inv((Ptr) txend_add, sizeof(int), Cache_Type_ALL, TRUE);
	while(*(int*)txend_add!=1){//�����ͷ�����δȫ������ʱ���������մ�������
		Cache_inv((Ptr) txflag_add, sizeof(int), Cache_Type_ALL, TRUE);
		if(*(int*)txflag_add==1){//�ȴ����ͷ�������ɷ���
			Trans_sim();

			*(int*)txflag_add=0;
			Cache_wb((Ptr) txflag_add, sizeof(int), Cache_Type_ALL, TRUE);

			ACK_submit();

			rxflag=1;//���շ�ack�������
			Cache_wb((Ptr) &rxflag, sizeof(rxflag), Cache_Type_ALL, TRUE);
		}
		Cache_inv((Ptr) txend_add, sizeof(int), Cache_Type_ALL, TRUE);
	}

    for(i=0;i<data_frame_num;i++){//ͳ�ƶ�������֡����
    	if(Rx_record[i]==0)
    		num++;
    }
    printf("drop %d dataframe\n",num);
}

0 Zhao Shui over 12 years ago in reply to HRi

Intellectual 910 points

Hi, Haim

Thank you for your advice and I've tried as you tell.

When I set SW breakpoint,the program stops at the breakpoint,then I resume,it ends with a right consequence.

When I set HW breakpoint,It is exactly the same(corrected by RandyP's advice,in my first trial,HW breakpoint is not set successfully)

Is this telling some useful information?I'm still a bit confused.

Best Regards,

Zhao

0 RandyP over 12 years ago in reply to Zhao Shui

TI__Guru* 84110 points

Zhao,

If the program does not stop at the HW breakpoint, then the HW breakpoint is not setup correctly or that instruction is not executed. Make sure you have setup the HW breakpoint as a program address or instruction breakpoint and that the action is to halt the processor.

Regards,
RandyP

0 RandyP over 12 years ago in reply to RandyP

TI__Guru* 84110 points

Zhao,

1. It would be much more efficient to put all of the variable data that needs to be shared by the two cores into a struct that is aligned to the cache line size boundary, then issue a single Cache_wb when you are ready to flag the txend. The IPC module is also good for signalling with interrupts and passing information between CorePacs. Remember that the Cache_wb will write full lines, so it is best to group variables that need to be written back and especially to avoid having other variables in the same cache line that may be affected poorly by the Cache_wb side-effect.

2. When you observe txend in the memory browser, does the color of the display give you any hint whether the data is in cache or is written and not in cache? Observe it at the breakpoint, after the txend=1 instruction, after the Cache_wb() command when single-stepping after the breakpoint, and at the end when the fail occurs. How does the color coding vary between those, and is the correct value still in cache in the failing case or is it just gone? Also try setting the breakpoint after the Cache_wb() command or at some other points in the program to figure out where the problem is coming from.

Regards,
RandyP

0 Zhao Shui over 12 years ago in reply to RandyP

Intellectual 910 points

Hi，RandyP

I try to align txend to 128bit and it can run smoothly now,I'll try to put all the signal variable into one struct later.

Thank you for your advice☺,and it seems my bad habit of placing data everywhere will cause errors when using cache.

Best Regards,

Zhao

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need breakpoint while debug to let program goes smoothly in 6678