Other Parts Discussed in Thread: AM3517
Hi,
We've develop an AM3517 board with the video subsystem based on the logicpd AM3517 board. We've a problem activating the dvi output because there is a PLL that can't be locked. The dmesg output with the DSI debug enabled is:
[ 5.356048] OMAPFB: omapfb_init
[ 5.356567] OMAPFB: omapfb_probe
[ 5.356689] fbcvt: 800x600@60: CVT Name - .480M3-R
[ 5.361785] omapdss DSI: dsi_pll_calc
[ 5.366821] omapdss DPI: dpi_set_timings
[ 5.366851] OMAPFB: create 1 framebuffers
[ 5.366882] OMAPFB: fb_infos allocated
[ 5.366882] OMAPFB: allocating 6291456 bytes for fb 0
[ 5.376129] mmc0: new high speed SD card at address 1234
[ 5.385284] mmcblk0: mmc0:1234 SA02G 1.83 GiB
[ 5.400451] mmcblk0: p1 p2
[ 5.427581] OMAPFB: allocated VRAM paddr 8ee00000, vaddr d1000000
[ 5.427612] OMAPFB: region0 phys 8ee00000 virt d1000000 size=6291456
[ 5.427642] OMAPFB: fbmems allocated
[ 5.427947] OMAPFB: check_fb_var 0
[ 5.427978] OMAPFB: max frame size 6291456, line size 1600
[ 5.427978] OMAPFB: xres = 800, yres = 600, vxres = 800, vyres = 600
[ 5.428009] OMAPFB: set_fb_fix
[ 5.428070] OMAPFB: fb_infos initialized
[ 5.430450] OMAPFB: framebuffers registered
[ 5.430511] OMAPFB: apply_changes, fb 0, ovl 0
[ 5.430511] OMAPFB: setup_overlay 0, posx 0, posy 0, outw 800, outh 600
[ 5.430541] OMAPFB: paddr 8ee00000, vaddr d1000000
[ 5.430572] omapdss OVERLAY: check_overlay 0: (0,0 800x600 -> 800x600) disp (800x600)
[ 5.430603] OMAPFB: create_framebuffers done
[ 5.430633] omapdss MANAGER: omap_dss_mgr_apply(lcd)
[ 5.430755] omapdss OVERLAY: check_overlay 0: (0,0 800x600 -> 800x600) disp (800x600)
[ 5.430877] omapdss CORE: restore context
[ 5.431060] omapdss MANAGER: configure_overlay(0)
[ 5.431091] omapdss DISPC: dispc_setup_plane 0, pa 8ee00000, sw 800, 0,0, 800x600 -> 800x600, ilace 0, cmode 40, rot 0, mir 0
[ 5.431121] omapdss DISPC: calc_rot(0): scrw 800, 800x600
[ 5.431152] omapdss DISPC: offset0 0, offset1 0, row_inc 1, pix_inc 1
[ 5.431152] omapdss DISPC: 0,0 800x600 -> 800x600
[ 5.431243] omapdss DISPC: fifo(0) low/high old 960/1023, new 960/1023
[ 5.431274] omapdss DISPC: dispc_enable_plane 0, 1
[ 5.431304] omapdss MANAGER: configure_manager(0)
[ 5.431396] omapdss MANAGER: configure_manager(1)
[ 5.431518] omapdss CORE: save context
[ 5.431640] omapdss MANAGER: omap_dss_mgr_apply(tv)
[ 5.431671] omapdss CORE: restore context
[ 5.431762] omapdss CORE: save context
[ 5.431854] OMAPFB: mgr->apply'ed
[ 5.431915] omapdss CORE: restore context
[ 5.432067] omapdss DSI: PLL init
[ 5.432159] omapdss DSI: PLL init done
[ 5.432189] omapdss DISPC: onoff 0 rf 0 ieo 0 ipc 0 ihs 0 ivs 0 acbi 0 acb 0
[ 5.432220] omapdss DSI: DSI clock info found from cache
[ 5.432250] omapdss DSI: dsi_pll_set_clock_div()
[ 5.432281] omapdss DSI: DSI Fint 1625000
[ 5.432281] omapdss DSI: clkin (dss2_fck) rate 13000000, highfreq 0
[ 5.432312] omapdss DSI: CLKIN4DDR = 2 * 284 / 8 * 13000000 / 1 = 923000000
[ 5.432312] omapdss DSI: Data rate on 1 DSI lane 461 Mbps
[ 5.432342] omapdss DSI: Clock lane freq 230750000 Hz
[ 5.432342] omapdss DSI: regm3 = 13, dsi1_pll_fclk = 71000000
[ 5.432373] omapdss DSI: regm4 = 0, dsi2_pll_fclk = 0
[ 5.480163] omapdss DSI error: cannot lock PLL
[ 5.484985] omapdss DSI: PLL uninit done
[ 5.484985] omapdss CORE: save context
[ 5.485107] omapfb omapfb: Failed to enable display 'dvi'
[ 5.490875] OMAPFB: free_resources
[ 5.497924] OMAPFB: free all fbmem
[ 5.498168] omapfb omapfb: failed to setup omapfb
[ 5.503204] omapfb: probe of omapfb failed with error -5
We can boot with the same SD card on the logicpd board and the 'omapdss DSI error: cannot lock PLL' error message don't appear and we can get video output on the monitor. Then, I've narrowed down the error to the code, in the linux-2.6.37 file : drivers/video/omap2/dss/dsi.c line 1066
if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
DSSERR("cannot lock PLL\n");
r = -EIO;
goto err;
}
It seems that the code is waiting until the bit 1 (DSI_PLL_LOCK) from the DSI_PLL_STATUS register is set. I would like to know which device, signal, etc is the responsible to set this bit because I can't found any external pin to do this, it seems that the AM3517 is doing some internal procedure to synchronize a PLL with some internal clock. Is there any register that I can read in order to get more information to know the reason of the problem?
I've read some configuration values before wait for the lock that maybe can help...
DSI_PLL_CONFIGURATION1: 0x611C0F
DSI_PLL_CONFIGURATION2: 0x10200C
DSI_PLL_STATUS: 0x41
DSI_IRQSTATUS: 0x200
Any help is welcome!
Jorge
