Cannot start C6657 in PCIe boot mode

We connected  JTAG emulator to both EVMs (bata and Prod) and check the PC and DEVSTAT register.

On both EVMs DEVSTAT register is set to 0x11809 (PCIe enabled, 100mhz clk, PCIe boot mode, little endian), but PC is different.

On Beta board PC points to L2 memory:

00800742:   100D                LDW.D2T2      *B4[0],B0
00800744:   6C6E                NOP           4
00800746:   A1FB         [!B0]  BNOP.S2       0x80074e,5
00800748:   10056013            CALLP.S2      0x803240,B3
0080074c:   EC47     ||         MV.L2         B0,B31
0080074e:   04A6                MVK.L1        0,A1
00800750:   8072                MVK.S1        100,A0
00800752:   2490     ||         ADD.L1        A1,1,A1
00800754:   2C48                CMPLTU.L1     A1,A0,A0
00800756:   007A         [!A0]  BNOP.S1       0x800742,0
00800758:   8C6E                NOP           5
0080075a:   020A                BNOP.S1       0x800750,0

On production board PC is 0x20B010B0


20b0109c:   E4000000            .fphead       n, l, W, BU, nobr, nosat, 0100000b
20b010a0:   D246                MV.L1X        B4,A6
20b010a2:   2212     ||         MVK.S1        1,A4
20b010a4:   02282228            MVK.S1        0x5044,A4
20b010a8:   0200C269            MVKH.S1       0x1840000,A4
20b010ac:   2426     ||         MVK.L1        1,A0
20b010ae:   0004                STW.D1T1      A0,*A4[0]
20b010b0:   0001E000            IDLE
20b010b4:   019A1028            MVK.S1        0x3420,A3
20b010b8:   01905868            MVKH.S1       0x20b00000,A3
20b010bc:   E1200001            .fphead       n, l, W, BU, nobr, nosat, 0001001b
20b010c0:   02000C2A            MVK.S2        0x0018,B4
20b010c4:   000C1362            B.S2X         A3
20b010c8:   01846162            ADDKPC.S2     0x20b010d0,B3,3
20b010cc:   D246                MV.L1X        B4,A6
20b010ce:   0212     ||         MVK.S1        0,A4
20b010d0:   000403E2            MVC.S2        CSR,B0
20b010d4:   000000CA            CLR.S2        B0,0,0,B0
20b010d8:   008003A2            MVC.S2        B0,CSR
20b010dc:   E1000040            .fphead       n, l, W, BU, nobr, nosat, 0001000b
20b010e0:   0C6E                NOP           1
20b010e2:   2427                MVK.L2        1,B0
20b010e4:   020003A2            MVC.S2        B0,IER
20b010e8:   00000000            NOP           
20b010ec:   02A803A2            MVC.S2        B10,ISTP
20b010f0:   6577                LDW.D2T1      *++B15[2],A10
20b010f2:   71F7                LDW.D2T2      *++B15[2],B3
20b010f4:   4C6E                NOP           3
20b010f6:   7577                LDW.D2T2      *++B15[2],B10

What would cause bootloader to take different execution path on production EVM?

Thank you

Dmitri Krivchitch

Hi

Any response on this problem would be appreciated

Thanks.

Dhar

The first thing I would recommend is to update the production EVM board IBL and factory default images.  This can be done by downloading the latest MCSDK at:

http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

then run the program_evm script found in the following directory: C:\ti\mcsdk_2_01_02_05\tools\program_evm

Once you do this, run the POST and make sure that runs, then try the PCIe boot again.  If you haven't already done so, this may fix it as I believe there was an issue with IBL.  At the same time, I will ping some other folks too.

Regards,

Travis

Hi Travis,

Thank you for the reply.

We updated both EEPROM images 0x50 and 0x51 with the latest images. That did not make any difference for the PCIe boot mode. The production EVM still stays at the same idle instruction

20b010b0:   0001E000            IDLE

Arun in http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/216539.aspx said " the FPGA in the EVM is programmed to boot to I2C no matter what boot mode is set and then jumps to the PCIe boot"

Is it possible that there is a problem with the FPGA and there is no jump to the PCIe boot ?

Best regards,

Dmitri Krivchitch

Dimitri,

Can you just connect both the EVMs and check the PC before you start booting?  This might give us a clue about the the FPGA version. Also did you run POST on failing EVM? Did they work?

Thanks,

Arun.

Also you can also run the POST in both the EVMs. The POST prints out the FPGA version. That will also gives us a clue.

Thanks,

Arun.

Hi Arun,

On both boards after reset PC is 0x20b00000.

Below is full POST output  for both EVMs.

1. Working Beta

TMDXEVM6657L POST Version 01.00.00.01
------------------------------------------
SOC Information

FPGA Version: 000F
Board Serial Number: 0002
EFUSE MAC ID is: 08 00 28 32 95 2B
PLL Reset Type Status Register: 0x00000001
Platform init return code: 0x00000000
Additional Information:
   (0x02350014) :0BEF0000
   (0x02350624) :000211FF
   (0x02350678) :00123400
   (0x0235063C) :000801FF
   (0x02350640) :000801FF
   (0x02350644) :000900DB
   (0x02350648) :000A40DB
   (0x0235064C) :000B10DB
   (0x02350650) :000C00DB
   (0x02350654) :000C00DB
   (0x02350658) :000C00DB
   (0x0235065C) :000D1800
   (0x02350660) :000E1800
   (0x02350668) :000F1800
   (0x02350670) :00101800
   (0x02620008) :0200200D
   (0x0262000c) :040101A7
   (0x02620010) :00000000
   (0x02620014) :4E3E0000
   (0x02620018) :0B97A02F
   (0x02620180) :0602F000
------------------------------------------

Power On Self Test

POST running in progress ...
POST I2C EEPROM read test started!
POST I2C EEPROM read test passed!
POST SPI NOR read test started!
POST SPI NOR read test passed!
POST EMIF16 NAND read test started!
POST EMIF16 NAND read test passed!
POST EMAC loopback  test started!
POST EMAC loopback  test passed!
POST external memory test started!
POST external memory test passed!
POST done successfully!

POST result: PASS

2. Production EVM with PCIe problem

TMDXEVM6657L POST Version 01.00.00.06
------------------------------------------
SOC Information

FPGA Version: 0010
Board Serial Number: 1237200
EFUSE MAC ID is: 00 18 30 06 91 D3
PLL Reset Type Status Register: 0x00000001
Platform init return code: 0x00000000
Additional Information:
   (0x02350014) :0BEF0000
   (0x02350624) :000211FF
   (0x02350678) :00123400
   (0x0235063C) :000801FF
   (0x02350640) :000801FF
   (0x02350644) :000900DB
   (0x02350648) :000A40DB
   (0x0235064C) :000B10DB
   (0x02350650) :000C00DB
   (0x02350654) :000C00DB
   (0x02350658) :000C00DB
   (0x0235065C) :000D1800
   (0x02350660) :000E1800
   (0x02350668) :000F1800
   (0x02350670) :00101800
   (0x02620008) :03009013
   (0x0262000c) :040101A8
   (0x02620010) :00000000
   (0x02620014) :09140020
   (0x02620018) :0B97A02F
   (0x02620180) :0602F000
------------------------------------------

Power On Self Test

POST running in progress ...
POST I2C EEPROM read test started!
POST I2C EEPROM read test passed!
POST SPI NOR read test started!
POST SPI NOR read test passed!
POST EMIF16 NAND read test started!
POST EMIF16 NAND read test passed!
POST EMAC loopback  test started!
POST EMAC loopback  test passed!
POST external memory test started!
POST external memory test passed!
POST done successfully!

POST result: PASS

Best regards,

Dmitri Krivchitch

Dimitri,

One more question. Are you booting the EVM from another EVM or from a linux host?

thanks,

arun.

Hi Arun,

We are booting from a vxWorks host.

We see difference in execution thread even when EVM is not connected to the host (switches still set for PCIe boot mode).

Beta EVM is running from LL2 and monitors magic address, while prod EVM is sitting at IDLE instruction.

Best regards,

Dmitri Krivchitch

Dimitri,

Sorry for the delay. What is the current status. Are you still having htis probelm?

Thanks,

Arun.

Hi Arun

We are still waiting for guidance on this problem. so far we have no solution to the problem.

Thanks

Dhar

HI Dhar,

I found out that the ROM PCIe boot has some issues working with the ATX computer platforms. In your caase the beta board still uses the IBL work around that we had in C6678 and C6670. For production boards, they removed this. I am trying to see what kind of work around is availbel for this. I will update it today as I have the meeting with the internal team on this.

Thanks for your patience.

Arun.

Hi Arun,

Thank you for the update.

We are designing our custom board where c6657 DSP will be loaded via PCIe interface. If ROM PCIe boot has a problem we need to know if there is a workaround that we can use on our board to be able to boot DSP in PCIe mode.

We have a very limited time to find a solution as schematics are pretty much complete and we are starting layout.

Best regards,

Dmitri Krivchitch

Dmitri,

I am trying to get you the options by end of this week.

Thanks so much for your patience.

Thanks,

Arun.

HI Dimitri,

I am scheduling an internal meeting today. Will get back to you once we have a solution ASAP.

Thanks,

Arun.

Hi Tsuomu,

You solution worked on the production board (TMDSEVM6657LS) we have in house.

Generating MSI interrupt after codeis loaded via PCIe wakes up the board and starts code execution.

Thnk you very much,

Dmitri Krivchitch

Thanks Furuse. I completely forgot that. 

Thanks,

Arun.