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C6657/5 SPI Boot Speed ( Can it operate faster ? )

larry bernstein
Intellectual 280 points

Hi,  I wanted to understand if the there is some way to decrease the boot time  ( ideally  by 2 x   to 4 x)  needed to read in the  ~4MB of app code.  We are using the  TMSDSEVMC6657 where we are  setting the DIP SW so  boot mode is SPI . The RBL first reads in the SPI Boot Parameter Table  at a slow clock rate  ( ~654KHz).  This is not a issue  since the  SPI Boot Parameter Table is small.   One of the parameters in the  SPI Boot Parameter Table is to set  the SPI Bus Speed and we are currently setting this to 50Mhz.   Once the SPI Boot Parameter Table is complete ,   the Boot Table data is being clocked by  RBL at   ~56MHz  ( this part is good)   but we are seeing  ~ 517usec delay between each byte  being read in.   The scope image  ( see SPI Boot Boot Table.jpg  attached) , illustrates the behavior.   Is there some way to decrease or eliminate the 517usec delay ( latency) between successive SPI byte reads of the 4MB of code or is there inherent to the RBL operation ?  Thank you

Larry

For reference,   at the bottom of this note is the SPI Boot Parameter Table data we are using.

 boot_mode = 50
 param_index = 0
 options = 1
 core_freq_mhz = 1000
 next_dev_addr_ext = 0x0
 sw_pll_flags = 1
 sw_pll_mult = 19
 sw_pll_prediv = 0
 sw_pll_postdiv = 0
 addr_width = 24
 n_pins = 4
 csel = 0
 mode = 2
 c2t_delay = 0
 bus_freq_mhz = 50
 bus_freq_khz = 0
  • 0
    Intellectual 865 points

    I'm working on the same project with Larry and I thought I'd post some scope captures showing the performance we are witnessing when we SPI Boot our app from NOR.

    Here's a snapshot of the RBL SPI Read clocking frequency ~50 Mhz (49.8ns clock interval)...

    Here's a snapshot of RBL SPI Read Inter-byte delay of 570ns causing our performance concern...

    -George

  • 0 in reply to George Lathrop
    Intellectual 865 points
    I restored the EVM back to the OOB web app which boots from NOR and I see the SPI Read clocking frequency to be ~20Mhz (49.8ns clock interval) and an inter-byte latency of ~616ns.
    Attached are the scope captures showing these measurements.
    Here's a snapshot of the RBL SPI Read clocking frequency ~20 Mhz (49.8ns clock interval)...


    Here's a snapshot of RBL SPI Read Inter-byte delay of 570ns...


    It appears that this performance is largely equivalent (if not a bit worse) than the RBL SPI Boot performance we're witnessing (previous post).
    This does *not* even begin to come close to TI's 57 Mbps (~7.125 MBps) stated performance for SPI on C665x.  Is this really achievable?
    -George
  • 0 in reply to George Lathrop
    Intellectual 865 points

    All,

    The first snapshot (two posts prior to this one) was labeled incorrectly.  It was actually a ~20 Mhz frequency (not 50 Mhz as stated) taking place during the RBL SPI Read transfers of the SPI Boot Parameter Table.

    Here's a snapshot of the ~56 Mhz (17.8 ns clocking interval) SPI Read transfer being perform by the RBL when loading the Boot Table.  The SBI Boot Parameter Table is telling the RBL to use the higher 50 Mhz SPI clocking frequency albeit we're witnessing the ~56 Mhz performance.  Yet another mystery...

     

    -George

  • 0 in reply to George Lathrop
    Intellectual 865 points

    All,

    I am truly sorry for the confusion here, but the first snapshot posting (now 3 posts ago) is apparently yet another SPI read of the OOB app.  Notice the similarity to the subsequent OOB snapshots.

    Here's is the ~654 Khz (1.53 us clocking interval) of the RBL's SPI read transfers of our SPI Boot Parameter Table...

    -George

  • 0 in reply to George Lathrop
    Intellectual 865 points

    Hi,

    Refering to the SPRABK5A "Throughput Performance Guide for C66x KeyStone Devices" it clearly states the theoretical SPI performance to be 66 Mbps and the maximum achievable data rate being 57 Mbps via EDMA.  Here's the excerpt...

    The question here is in regards to the C6655/7 RBL's SPI Boot performance.  As demonstrated with the previously posted screen scope captures of our SPI Boot, it appears that we are *not* coming anywhere near TI's stated performance of 57 Mbps (7.125 MBps).  The actual performance being witnessed in our RBL's SPI Boot is ~1.3 MBps.  As you can see the byte-to-byte SPI Read interval is (142ns + 570ns = 712ns).  This is 5x slower that expected maximum.

    Is this ~1.3 MBps SPI data transfer rate to be expected during the C6655/7 RBL's SPI Boot?

    -George