C6747 Cache L1P,L1D, L2 work well?

Hello,

Some suggested answers:

1. The C67x+ core can execute up to 8 instructions (ie one 8x32=256-bit fetch packet) at each cycle, one instruction per unit (L1, L2, D1, D2, S1, S2, M1, M2), hence the 256-bit path width between CPU and L1P cache/memory.

2. The C67x+ can access up to two 64-bit words of data per cycle (through D1 & D2 units), hence the dual 64-bit path width between L1D cache/memory. When cache hit, the CPU gets what it asked (from 1 byte to two 64-bit words). When cache miss, a full cache line is read from L2 or external memory before program resumes (moreover, an old line may be written).

3. The cache line size is only required to be a multiple (power of 2) of the data path width. The bigger the line size is, the easier is the cache to manage (less cache entries), but the longer is the line load/save process.

4. L1D and L2 caches can be independantly enabled/disabled. Depending on program, disabling L1D may considerably slower execution, especially for intensive data processing programs over L2 (the 256-bit data path between L1D cache and L2 is wasted), while the relative impact is less with external and slower memory like mDDR/DDR2.

5. No answer

Jakez

thanks jakez，

I understand a basic information:

        1.       operation between CPU and Cache  is path width; operation between Cache and lower memory is cache line size.

        2.       line size is required to be a multiple (power of 2) of the data path width.

but I have some question on your answers

      2 ".........When cache miss, a full cache line is read from L2 or external memory before program resumes (moreover, an old line may be written).", the cycle counts of

      a full cache line read from L2 or external memory is more than the cycle counts of he CPU gets what it asked(such as just 1 byte). Does this called Cache penalty?

      how to understand Cache penalty?Does it mean Cache memory system worse than no cache system sometimes?

      During the situation if I disable L1D cache, Cpu get what it asked directly from L2, does it more quick?

new question:

      1.    I have my program, which the bin file is 350Kbyte, and I enable L1D cache and L1P cache only, configure L2 whole  as SRAM with a 2M byte external SDRAM

            I  put all code into SDRAM, all data and task stack into L2 SRAM, how to update my program perfomance?

      2.   if my program only size 120Kbyte, how can I configure the cache and memory layout to make the program memory access performance best?I will put all code        and  data into L2 SRAM.

      3.  does L1D cache(4k) can Cache L1D RAM and does L2 Cache(64KB) can cache L2 SRAM else?

Hello Thomas,

Suggested answers to your questions about my answers:

2. Yes, a full line read (atomic cache controller element) is done for a single byte read when cache miss, which can take of course much more time than a single uncached byte read. You can call this cache penalty; reducing line size would reduce the penalty, but the cache controller would be more complex. A lot of DSP algorithms work locally with relatively small data blocks, making the cache usage very profitable overall. On the other hand, some algorithms doing random access on big data blocks (much greater than cache capacity) may be much slower with cache active than without. In a general way when seeking for optimal performance, algorithms may have to be redesigned to operate on sub-blocks of adequate size.

I don't think you can speed up significantly a single word read from L2 by disabling L1D, since L1D line size is equal to L1/L2 data path width.

You can take a look on this recent post: http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/234211/822241.aspx#822241

Suggested answers to your new questions :

1. Depending on your program; if mainly loops, L1P cache is effective, nothing to do in the general way. Another ways:

You can put critical code in L1P memory and critical data in L1D memory (L1P & L1D as partial caches).

You can use EDMA / IDMA to move data in background and optimize memory bandwidth.

You can think about using the 128KB L3 RAM (faster than DDR2).

You can use the MARn registers to disable caching on selected DDR2 regions you would reserve for rarely accessed data, avoiding useless cache line load.

...

2. Same answer as 1: no general answer, it's up to you to identify critical code and optimize it

3. L1D cache does not cache L1D memory, and L2 cache does not cache L2 memory (I hope, it would be a wasting of resources); when both are active, L1D cache is always a subset of L2 cache.

Jakez

hi Jakez

I do not understand what exact is miss pipeling?can you explain detail to me, thank you!

and  I want to debug the cache usage, but the Cache tag viewer does not work well, and the cache is not showing.

Hello,

Presuming you worry about L1D pipelining of read misses, see 3.1.2 of spru82a.pdf (see also sprufk5.pdf).

In other words (maybe clearer, maybe not - residual translation errors possible):

With high clock frequency synchronous systems, you can achieve high speed data read but some latency cycles are needed for each transfer in order to pass synchronization stages to RAM and back from RAM (control/data clocks synchronizers, RAM bufferization,...). A single 256-bit word read from L2 RAM to L1D cache takes also 10.5 CPU cycles (1/2 cycle probably because rising and falling edges of main clock are used in synchronization). When issuing consecutive reads, the commands can be pipelined : the first read takes 10.5 cycles, the other pipelined reads take only 3 cycles more each. The (peak or commercial) bandwidth of data read from L2 RAM is then 256/3*freq(CPU) bits, more than 3 times the bandwidth for sporadic reads. The pipelining miss is disrupted when a write to L2 is issued. It's unclear (for me) if a NOP (no read, no write) can disrupt the miss pipelining (TI specialists required). Note that reads from L2 cache take more time than reads from L2 RAM (cache controller stuff adds latency and reduces peak bandwidth): latency is 12.5, pipelined period is 7 cycles.

The TI example in spru82a (L1 touch function) illustrates this. By using this function which does "dummy" reads (but strategic parallel pipelined reads), you load data from L2 to L1D cache with maximum efficiency, before doing calculations on the data. From some minimal data size, the execution time of this function is less than the overhead that would be generated by the cache misses during the calculations in a "normal" scheme (starting with an empty L1D cache).

Still no answer about cache & debug in CCS

Jakez