C5504 Asynchronous SRAM interface

HRi

Hi,

- I assume that in the C5504 User Guide Table 6-20 "EMIF Asynchronous Memory" in the case of SYSCLK = 150MHz E is equal to 6.66nS is that correct?

- Does the Asynchronous SRAM have the SDRAM 100MHz limitation?

- Can I change the Asynchronous SRAM parameters during system operation?

Thanks,

over 12 years ago

0 HRi over 12 years ago

Guru 10750 points

Anyone.....

0 Steve Tsang over 12 years ago in reply to HRi

TI__Mastermind 23785 points

Sorry to response late.

Yes. In the case of SYSCLK = 150MHz E is equal to 6.66nS.

What is system operation? It is described in Section 1.2.7.3 in EMIF User's Guide, http://www.ti.com/lit/ug/sprugu6a/sprugu6a.pdf, that the EMIF's registers must be programmed prior to accessing the external memory. A transfer following a write to these registers will use the new configuration which recommends changing the parameters only between operations.

Hope this helps.

Regards.

0 HRi over 12 years ago in reply to Steve Tsang

Guru 10750 points

Steve,

Thank you,

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C5504 Asynchronous SRAM interface