Dear All,
I am working with a custom board using DM8148 TI CPU. For the first time, I try our board with ezsdk and the psp examples to test HDMI and DVO2 output. We success-ed to tie HDMI and DVO2 to display the graphic PIPE 0 by below setting:
echo 0 > /sys/devices/platform/vpss/graphics0/enabled
echo 0 > /sys/devices/platform/vpss/display0/enabled
echo 0 > /sys/devices/platform/vpss/display1/enabled
echo 1080p-30 > /sys/devices/platform/vpss/display0/mode
echo 1080p-30 > /sys/devices/platform/vpss/display1/mode
echo 74250,1920/88/148/44,1080/4/36/5,1 > /sys/devices/platform/vpss/display1/timings
echo 74250,1920/88/148/44,1080/4/36/5,1 > /sys/devices/platform/vpss/display0/timings
echo triplediscrete,rgb888 > /sys/devices/platform/vpss/display0/output
echo doublediscrete,yuv422spuv > /sys/devices/platform/vpss/display1/output
echo 5 > /sys/devices/platform/vpss/system/tiedvencs
echo 2:hdmi,dvo2 > /sys/devices/platform/vpss/graphics0/nodes
echo 1 > /sys/devices/platform/vpss/display0/enabled
echo 1 > /sys/devices/platform/vpss/display1/enabled
echo 1 > /sys/devices/platform/vpss/graphics0/enabled
fbset -xres 1920 -yres 1080 -vxres 1920 -vyres 1080
After that, We moved to develop software base on RDK 3.2 with MCFW framework and We got troubles here.
As I knew, the setting for display could be done in these code files:
links_m3vpss\system\system_dctrl.c:
Vps_DcConfig gSystem_dctrlTriDisplayConfig = {
VPS_DC_USERSETTINGS, /* Use Case */
/* Edge information */
{
{VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX} ,
{VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
{VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
{VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND} ,
{VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX} ,
{VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND} ,
{VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND} ,
{VPS_DC_GRPX0_INPUT_PATH, VPS_DC_DVO2_BLEND} ,
{VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},
{VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
{VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX},
{VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX},
}
,
12,
/* VENC information */
{
/* Mode information */
{
// Bioz
//{VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
{VPS_DC_VENC_HDMI, {FVID2_STD_1080P_30}
// ~Bioz
}
, /* 1080p30 is mode
* is overwritten
* later inside
* System_displayCtrlInit
// Bioz */
//{VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
{VPS_DC_VENC_DVO2, {FVID2_STD_1080P_30}
// ~Bioz
}
, /* 1080p30 is mode
* is overwritten
* later inside
* System_displayCtrlInit
*/
{VPS_DC_VENC_SD, {FVID2_STD_NTSC}
}
}
,
(VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2), /* Tied VENC bit
* mask */
3u /* Number of VENCs
*/
}
};
Int32 System_displayCtrlInit(VDIS_PARAMS_S * pPrm)
{
...
dctrlTriDisplayConfig = &(gSystem_dctrlTriDisplayConfig);
dctrlTriDisplayConfig->vencInfo.tiedVencs = pPrm->tiedDevicesMask;
...
}
mcfw_api\ti_vdis.c:
Void Vdis_params_init(VDIS_PARAMS_S * pContext)
{
...
// Bioz
#if 0
pContext->deviceParams[i].resolution = VSYS_STD_1080P_60;
#else
pContext->deviceParams[i].resolution = VSYS_STD_1080P_30;
#endif
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_DOUBLECHAN_DISCSYNC;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dataFormat = SYSTEM_DF_YUV422SP_UV;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_EMBSYNC;
pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;
...
}
multich_usecase\ti_mcfw_ipnc_main.c:
vdisParams.deviceParams[VDIS_DEV_HDMI].resolution = VSYS_STD_1080P_30;
vdisParams.deviceParams[VDIS_DEV_DVO2].resolution = VSYS_STD_1080P_30;
Vdis_tiedVencInit(VDIS_DEV_DVO2, VDIS_DEV_HDMI, &vdisParams);
Just only HDMI output worked, the DVO2 didnot work. It look like the HDMI and DVO2 was not tied together correctly.
I checked the system/tiedvenc, I always saw 0 and the graphics0/nodes always 1:HDMI.
I will be very grateful if you can help me to figure out my mistake or give me some hint for solving this problem.
