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AM335x Sitara configurable as I2S Master with 24MHz MAIN_OSC_CLK ?

Klaus Liebschner
Intellectual 595 points

Hello Community,

I am working on the BeagleBone Board and want to receive an I2S audio Stream via McASP0 via the Receive Clock Generator Block (ACLKR pin configured as output) on page3963 of SRPUH73F.As the BB has a MAIN_OSC_CLK of 24MHz and the dividers HCLKRDIV and CLKRDIV are integers only for the ACLKR pin, a multiple frequency of 48kHz for the I2S clock can not be generated.

Is there any other solution / backdoor / idea to configure the Sitara anyway as Master ?

Please let me know, Klaus