Use AM3359's timer trigger the edma3 transmiter problem.

Fllow the source clip:

#define EDMA3_CHA_TIMER4              48

static void EDMA3INTCConfigure(void) {    

   /* Initializing the ARM Interrupt Controller. */    

   IntAINTCInit();

    /* Registering EDMA3 Channel Controller 0 transfer completion interrupt.  */    

   IntRegister(SYS_INT_EDMACOMPINT, Edma3CompletionIsr);

    /* Setting the priority for EDMA3CC0 completion interrupt in AINTC. */    

   IntPrioritySet(SYS_INT_EDMACOMPINT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Registering EDMA3 Channel Controller 0 Error Interrupt. */    

   IntRegister(SYS_INT_EDMAERRINT, Edma3CCErrorIsr);

    /* Setting the priority for EDMA3CC0 Error interrupt in AINTC. */    

   IntPrioritySet(SYS_INT_EDMAERRINT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the EDMA3CC0 completion interrupt in AINTC. */    

   IntSystemEnable(SYS_INT_EDMACOMPINT);

    /* Enabling the EDMA3CC0 Error interrupt in AINTC. */    

   IntSystemEnable(SYS_INT_EDMAERRINT);

}

static void EDMA3Initialize(void)

{    

 /* Initialization of EDMA3 */    

 EDMA3Init(SOC_EDMA30CC_0_REGS, EVT_QUEUE_NUM);

    /* Enabling IRQ in CPSR of ARM processor. */    

IntMasterIRQEnable();

    /* Configuring the AINTC to receive EDMA3 interrupts. */    

EDMA3INTCConfigure();

    // Request DMA Channel and TCC for UART Receive    

EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,          EDMA3_CHA_TIMER4, EDMA3_CHA_TIMER4,                         EVT_QUEUE_NUM);

}

static void TimerEDMAConfTransfer(unsigned int tccNum,                                   

                                                        unsigned int chNum,                                   

                                                       volatile unsigned char *rxBuffer,                                   

                                                        unsigned int length)

{    

EDMA3CCPaRAMEntry paramSet;

    /* Fill the PaRAM Set with transfer specific information */    

paramSet.srcAddr = (unsigned int) DataSrc;    

paramSet.destAddr = (unsigned int) rxBuffer;

    /* A, B and C Count values. */    

paramSet.aCnt = (unsigned short)length;    

paramSet.bCnt = (unsigned short)1;    

paramSet.cCnt = 1;

    paramSet.srcBIdx = 1;    

paramSet.srcCIdx = 0;    

paramSet.destBIdx = 1;    

paramSet.destCIdx = 0;

    paramSet.linkAddr = 0xffff;    

paramSet.bCntReload = 0;

    paramSet.rsvd = 0;

    /* OPT PaRAM Entries. */    

paramSet.opt = 0x00000000u;

    /* Source and Destination addressing modes are Incremental. */

    /* AB Synchronized Transfer. */    

paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);

    /* Setting the Transfer Complete Code(TCC). */    

paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);

    /* Enabling the Completion Interrupt. */    

paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);

    /* Now write the PaRAM Set */    

EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, &paramSet);

    TimerDummyPaRAMConfEnable();

    /* Enable EDMA Transfer */    

EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);

}

main()

{

Timer4IntRegister();

Timer4Config();

 TimerEDMAConfTransfer(EDMA3_CHA_TIMER4,        EDMA3_CHA_TIMER4,                       DataBuf1,                             32);  

Timer4IntEnable();

}