CORECLKp/n & DDRCLKp/n CLOCK Input Jitter Specificatons

Charles,

The two subject clocks are system clocks and not data transmission clocks, so there is not a BER value associated with them.

The types and description of these jitter values are found in the notes and text following the table and in the section after it. I personally could not offer a better explanation of these terms and values.

Are you having a tough time meeting these specifications in your custom board design?

Regards,
RandyP

Hi RandyP -

I was hoping for more detailed information about the magnitude vs frequency of interest much like the serial clock inputs (ie. PCIe). 

Also, are the system clocks jitters just cycle 2 cycle , Time Interval Error or Total jitter which have a BER component.  The uppermost title bar footnotes say

Total Jitter. 

Charles,

The SERDES reference clocks are specified in detail in section 3.5.7 which includes variations for clock rate, data rate and BER.  These SERDES clocks have very tight jitter requirements and frequency content is significant.  The non-SERDES reference clocks have much less restrictive jitter requirements as stated in the device's Data Manual.  The clock source for the Main PLL and the PA PLL can have up to 100ps of jitter, peak-to-peak.  The DDR PLL can have no more than 2.5% of the input reference period as the pk-pk limit.  These are long-term peak-to-peak limits as measured relative to a stable reference.

Tom

Tom -

Sounds great thank you....One final clarification, the HW spec (SPRABI2B) says that the input jitter on the DDR PLL is 2.5% of the DDRCLK OUTPUT

period.  The #4 footnote reference calculation is for what looks like a 800 MHz clocked DDR interface and yields an input jitter spec of 32.25 pS.

In my applicaton, our input clock is 51 Mhz and our output clock is 533 MHz.  Which one should I take 2.5% of to calcuate my allowable input jitter

Thanks!