• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 582 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

tool to convert gel file for CCS5.x (C66x dsp) to C or assembly

Weichun Yuan
Expert 1210 points
Other Parts Discussed in Thread: TMS320C6657

We are trying to bring up our C6657 based system and we are debugging the gel file, in particular for DDR configuration. Is there a tool which can translate the gel file into source code (c or assembly) for us to use for device initiation so that we do not have to manually copy and paste the register and numbers?

  • 0
    TI__Mastermind 30825 points

    No, there is not a way to translate this to C other than by hand.  That said, you need to follow the programming sequence defined in the DDR User Guide to program the DDR correctly.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Guru 10750 points

    Hi Yuan,

    You can see the device initialization example under pdk_C6678_1_1_2_5\packages\ti\platform\evmc6678l\platform_lib\src\platform.c function platform_init and pdk_C6678_1_1_2_5\packages\ti\platform\evmc6678l\platform_lib\src\evmc6678.c function DDR3Init

    Thanks,

    HR

  • 0 in reply to HRi
    Expert 1210 points

    Hi, HR and Chad,

    We are trying to bring up our C6657 based system by updating the gel file and the platform_init code based on pdk_C6657_1_1_1_4. We use a signle 16 bit DDR (MT41J128M8 – 16 Meg x 8 x 8 banks) instead of two 16 bit DDR. The gel file seems to work but we run into problems with the platform_init

    1. in gel file, we directly write 0x0010010F to DDR_DDRPHYC. But in DDR3Init() function in CSL_EMIF4F_SetPhyControl(ddrPhyCtrl,  ddrPHYReadLatency);is called and in additional to bit masking, we have an additional left shift of 5 bits. Could you please help us to understand this discrepancy?

    2. as described earlier, we use one single 16 bit DDR instead of two 16 bit DDR. We therefore change the NM to 2 to reflect the 16 bit bus as well as the row size to reflect that it has only 128M. Is there anything else we should change in addition to the timing? How about the burst size? Do we have to do anything to make sure that DSP use the right burst size?

    thanks

    Weichun

  • 0 in reply to Weichun Yuan
    TI__Mastermind 30825 points

    Weichun,

    Please review the Keystone DDR Initialization Application Note that is available on the TMS320C6657 <-- Product Page.  It will go through what is needed.  It will vary based on your board implementation (including routing and other details not provided.)  Hacking up the GEL file and rewriting this in C is not the best approach to take.

    Best Regards,
    Chad