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AM1808 addressing 256MBytes of mDDR

Other Parts Discussed in Thread: AM1808

Hi TI forum,

Can the AM1808 address 256MBytes of mDDR on 1 chip select?

On page 98 of the technical reference manual, it states that the DDR2/mDDR memory controller can address up to a 256MBytes memory address space for 16-bit mDDR.

And on page 325 is states that the DDR2/mDDR memory controller only has 1 chip select.

So is it safe to assume that the AM1808 can address up to 256MBytes on the 1 chip select?

Thanks,

Mike

  • Hello,

    Chip Select signal (DDR_nCS) is not related to capacity in mDDR/DDR2 interface. Moreover it's always low during normal operation.

    You may refer to byte select signals (DDR_DQM[1..0], DDR_DQS[1..0]) which permit to manage the two data bytes.

    Jakez

  • Thanks Jakez,

    I know that the chip select is not related to the capacity of the mDDR/DDR2 interface, but there is a direct relation as to how much mDDR/DDR2 you can interface to per chip select.

    Processors have a complete addressable memory range but the external memory interfaces are limited to the amount of memory that they can address, but which is expandable using chip selects.

    Thus I ask again, can the mDDR/DDR2 memory interface access 256MBytes directly using the 1 chip select?

    Thanks,

    Mike

  • Hi

    Yes it should be possible to have a single 16 bit or 2 8 bit DDR2/mDDR memory devices to get you to 256 Mbytes. Here are some quick calc on what the row/column/bank requirements would be

    (DDR2)
    Memory Data Bus Width # of Memories EMIF Data Bus Size row column bank total
    (MBYTES)
    Memory Density (Mbits)
                   
    16 1 16 14 10 8 256 2048
    1 16 14 11 4 256 2048
    8 2 16 14 10 8 256 1024
    2 16 14 11 4 256 1024
     (mDDR)
     Memory Data Bus Width # of Memories EMIF Data Bus Size row column bank total
    (MBYTES)
    Memory Density (Mbits)
                   
    16 1 16 14 11 4 256 2048
    8 2 16 14 11 4 256 1024