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Powering AM335x: designing issues.

Manuel Martinez Guillen1
Intellectual 270 points
Other Parts Discussed in Thread: TPS65910A

Hello,

We have some doubts about how to power the AM335x. For our design we're using as example the schematics of the beaglebone and the starter kit.

1. What PMIC is more suitable for a DDR3 design: TPS65217C or TPS65910A3?. We have not found any schematic example using the first one. Besides it is in stock only in one common distributor.

2. The schematic of the beaglebone shows one bypass capacitor per VDD_CORE and VDDS_DDR ball on the AM335x. However the schematic of the starter kit shows 19 capacitors per 7 VDDS_DDR balls and 5 capacitors per 19 VDD_CORE balls. It is a mistake?

3. Both designs use, mainly, one 0.01uF/0402 bypass capacitor per ball in all the rails. It is possible to change to 0.1uF/0201 and share 2 balls per via, in few cases, as propose the following wiki?:

http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling

4. Is there any documentation about the recommended stack-up? Our PCB will have 8L but we're not sure if using 2PowerP/GND or 1PP/3GND. We'd like to fanout all the nets.

5. Connected to the TPS65910A3 in the starter kit there are few zero ohm jumper: Can be removed? 

Thanks,

Manuel.

  • 0
    TI__Guru**** 393215 points
    Hi Manuel,
     
    1. What PMIC is more suitable for a DDR3 design: TPS65217C or TPS65910A3?. We have not found any schematic example using the first one. Besides it is in stock only in one common distributor.
     
    Both are suitable. The Beaglebone is designed with TPS65217C, never mind that it's marked as TPS65217B on the schematics.
     
    2. The schematic of the beaglebone shows one bypass capacitor per VDD_CORE and VDDS_DDR ball on the AM335x. However the schematic of the starter kit shows 19 capacitors per 7 VDDS_DDR balls and 5 capacitors per 19 VDD_CORE balls. It is a mistake?
    3. Both designs use, mainly, one 0.01uF/0402 bypass capacitor per ball in all the rails. It is possible to change to 0.1uF/0201 and share 2 balls per via, in few cases, as propose the following wiki?: http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling
     
    You should follow the recommendations in the AM335X Datasheet, Section 3.4 for quantity and values of bypass capacitors.
     
    4. Is there any documentation about the recommended stack-up? Our PCB will have 8L but we're not sure if using 2PowerP/GND or 1PP/3GND. We'd like to fanout all the nets.
     
    You should follow the recommendations in the AM335X Datasheet, Section 5.5.2.2 (if you use DDR2 memory) or Section 5.5.2.3 (if you use DDR3 memory) for stackup and memory design/decoupling/routing.
     
    5. Connected to the TPS65910A3 in the starter kit there are few zero ohm jumper: Can be removed? 
     
    Yes, these are for debug purposes. You can decide whether you need them. Make sure you don't hardwire any 0Ohm jumpers marked as DNI - these are not mounted on the Starter Kit PCB.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Biser,

    I will try to place as many capacitors as possible but is gonna be difficult to place 20, since the DDR3 is very close to the AM335x (2-3mm) and each power ball of the DDR3 have already his own bypass.

    Thanks by the info.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Biser,

    Please I need to be sure of two issues before finish the PCB:

    1. Is there any documentation, at least I can't find this, about how work the 2 AND gates connected to RTC_PORZ? I mean: I understand that the circuit is to make a delay and hold RTC_PORZ low until VRTC be stable but: how long must to be this delay? nanoseconds, miliseconds...? It is important where to place the AND gates in the PCB?.

    2. I don't understand why you say: "Make sure you don't hardwire any 0Ohm jumpers marked as DNI". Shouldn't be the opposite? For example: I2C PMIC control & I2C PMIC Smartreflex are connected by 2 jumpers marked as DNI and the hardware user guide says that both are available. Moreover, VRTC_PMIC (side of the PMIC) and VRTC(side of the AM335 and RTC reset circuit) are connected by a jumper marked as DNI: if I leave the connection in open-circuit  it wouldn't connection between VRTC and the PMIC.

    Thank you,

    Manuel.

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Hi Manuel,
     
    1. RTC_PORZ recommendation can be found in the AM335X Datasheet, Note A below Figure 4-1. The circuit you refer to doesn't fulfill this requirement. However, it's important first to establish whether you will need the AM335X internal RTC. For silicon Rev.1.0 there is an Errata Advisory 1.0.5, which you should check. This errata makes  RTC-only mode practically unusable for this silicon revision. This has been fixed in Rev.2.X silicon. If you don't intend to use the RTC you can tie RTC_PORZ to PORZ, making sure that PORZ is at 1.8V voltage level (RTC_PORZ is on the VDDS_RTC rail and PORZ is on the VDDSHV6 rail, however PORZ accepts 1.8V levels even if VDDSHV6 is at 3.3V). If you stick to the ref. design, it's not important where you place the NAND gates.
     
    2. I agree about the I2C jumpers (R137, R138 on the Starter Kit). However, for R23 you will notice that an external LDO is used to generate processor VRTC (U21 on the Starter Kit). This is related to the PMIC version being used (see http://www.ti.com/lit/ug/swcu093b/swcu093b.pdf). Also PMIC INT1 doesn't have to be connected to the processor.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Hi Biser,

    Really complicated to me :-(.

    1. We're not sure if we will use RTC-only mode or not but we would like, at least, to evaluate it in our prototypes: if it's not a really issue.

    A. DON'T USING RTC-only mode. I guess it won't be necessary to include the 32KHZ xtal, leave VSS_RTC floating or tie it to GND, as well as remove the AND gates circuit... and all should to work fine: am I wrong? What I don't understand is how to tie RTC_PORZ to PORZ when VDDSHV6 is at 3.3V, VRTC_POZ must to be driven high at 1.8V and PORZ is wired to nRESPOWERON of the PMIC which is in the VDDIO rail: referenced to VAUX33 (3.3V).

    B. USING RTC-only mode. In what silicon version works the AND gates circuit? 2.0?. We have stocked few old XAM3359 parts but is not an issue to buy new ones.

    2.

    A. We keep both I2C channels of the PMIC connected. Am I wrong?

    B. OK. I didn't notice that PMIC VRTC pin is and LDO. For some reason (timming issue I guees) it is not used to supply VRTC rail on the processor and instead of this is used an external LDO. So if we decide to use RTC-only mode we have to connect the side of the processor to the external LDO and the side of the PMIC (BOOT1 pin) to the internal PMIC LDO (pin 29). Am I wrong?.

    C. OK. I will disconnet PMIC_INT1 of the processor.

    Thanks again,

    Manuel.

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Hi Manuel,
     
    It's not that complicated, maybe I didn't explain it well enough.
     
    1A. Yes, you won't need the 32kHz crystal. VSS_RTC must be tied to GND. In this case you can make your PORZ signal at 1.8V level and tie together PORZ and RTC_PORZ, regardless of VDDSHV6 voltage. You can condition PORZ through a 3.3V tolerant buffer which is powered from VDDS_RTC. If you check the latest datasheet (Rev. E), you will see that PORZ treshold is validated at 1.35V (bottom of Table 3-11 at page 89).
     
    1B. RTC-only mode is fixed for silicon revisions 2.X, starting from 2.0.
     
    2A. Yes, both I2C channels should be connected.
     
    2B. The external LDO is necessary for A and A3 versions of TPS65910A. In OFF state these PMIC's switch their VRTC LDO in low power mode, which doesn't provide enough current for VDDS_RTC. The external LDO isn't necessary for A31 version of TPS65910A. Check http://www.ti.com/lit/ug/swcu093b/swcu093b.pdf, Table 1.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Hi Biser,

    I think now I understand it. Please confirm:

    1. VDSS_RTC must to be supplied even RTC-only mode is not used. Only A31 revision of the PMIC sources enough current to this rail, so for the rest of the versions it's necessary to use an external LDO.If RTC is not used it's enough tie RTC_PORZ and PORZ together and use a buffer powered from VDDS_RTC, for example a logic gate, to adapt nRESPOWERON signal from 3.3V to 1.8V since PORZ is validated from 1.35V. All right?

    2. If we maintain the AND gates circuit, RTC-only mode won't work properly if not used silicon revision from 2.x. For the rest the processor works fine. All right?

    We really appreciate the support,

    Manuel.

    Edited: I meant A31 instead of A3

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Hi Manuel,
     
    1. Correct.
    2. The AND gates you mean are the RTC reset circuit, right? They don't have anything to do with the silicon revision. The RTC-only mode issue, which is described in Errata Advisory 1.0.5, comes from the problem that the 32kHz clock gets gated off when processor VDD_CORE is off or PORZ is low. This issue is valid only for silicon Rev.1.0, and has been corrected in Rev.2.X. The effects from this issue are described in the Errata, but in summary RTC-only mode will not work for Rev.1.0 silicon. But the RTC_PORZ still has to be driven even if RTC isn't used (by tying it to PORZ). If RTC is used, then you can either apply the AND gate reset or use a 1-2ms delay reset supervisor from VDDS_RTC (see note A below Figure 4-1 in the datasheet). By the way, the 0.01uF capacitor C114 in the dual AND gate circuit should be replaced with 2.2uF for datasheet compliance (C114 is referring to EVM schematics Rev. 1.4A).
     
    Don't hesitate to ask further questions, this issue is a bit complicated and it's important that you get it right.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Hi Biser,

    We're going to leave the RTC reset circuit as it is now in prevision for the future (even if we mount old silicon revisions at this moment). Sorry I can't find the schematic you are doing reference: Is the capacitor you refer C191 in the starter kit? Now that you talk about it... I have not simulated this circuit but I tought that 0.01uF were a low value for a RC net of 1-2ms.... 

    Best regards,

    Manuel.

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Hi Manuel,
     
    The schematics can be downloaded from this link: http://processors.wiki.ti.com/images/d/d0/AM335X_gpevm_ZCZBASEBOARD_3H0002_REV1_4A.zip. And this is the wiki page for the EVM board files: http://processors.wiki.ti.com/index.php/AM335x_General_Purpose_EVM_Board_Design_Files. And yes, this capacitor will probably be changed to 2.2uF in future board releases.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    Biser,

    yes: is the same capacitor. Please one last question and I will stop bothering: GPIO_CKSYNC is pulled to VRTC (the external LDO),Would be possible to pull this to VRTC_PMIC? As I told you I had both rails connected by mistake and the change of this pull-up would make me work a lot?

    Thanks,

    Manuel.

  • 0 in reply to Manuel Martinez Guillen1
    TI__Guru**** 393215 points
    Sure Manuel, this shouldn't be a problem. 10kOhm pullup at 1.8V will sink 180uA at most. But I notice that on the EVM Rev.1.4A GPIO_CKSYNC is left floating, so you probably won't need this pullup.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 270 points

    I will leave it only just in case: in the Starter kit (newer design) stills pulled up. I hope this one be the last issue.

    Thanks a lot. Best regards,

    Manuel.