Hi,
The DM814x TRM, sec. 9.4.2.2 says that the CLKDIV parameter in the "MDIO Control (CONTROL) Register" is bits 15 downto 0. But the check in drivers/net/davinci_mdio.c is against 0xFF:
#define CONTROL_MAX_DIV (0xff)
....
static void __davinci_mdio_reset(struct davinci_mdio_data *data)
{
u32 mdio_in, div, mdio_out_khz, access_time;
mdio_in = clk_get_rate(data->clk);
div = (mdio_in / data->pdata.bus_freq) - 1;
if (div > CONTROL_MAX_DIV)
div = CONTROL_MAX_DIV;
Is it a coding bug, or should the divider really stay at 0xFF and below?
Dan -
