access nand flash when MMU and cache are enabled

Hi Jason,

Have you tried with disabling cache ? Please comment the function call "CacheDisable();" to check this.

Also, are you doing DMA or polling ? As you might be aware, when doing in DMA mode, we will need cache maintanance operations in place. I dont think you need to modify the page tables.

Regards,

Sujith

I also come aross the same problem. 

when enable the cahe all (both I-cache and D-cache) , i can read the nand correctly. but failed when i write the nandflash . 

In the other way , when i only enable the I-cache , it's OK for both reading and writing the nandflash. 

can you help me out of the problem ? because it's important for me to enable the cahe all . (for the speed reason)

Hi,

If you are doing DMA with Data Cache enabled, you need to invalidate the cache after completing DMA reception and clean the cache before enabling DMA transmission. You can refer to cache/mmu example provided with the package.

So the sequence for reception is :

1. DMA Completed interrupt/ mechanism to know that DMA receive is complete

2. Invalidate the cache (to make sure that next access is directly from the DMA'ed memory)

3. Read the buffer (now the read is not from the cache)

The sequence for transmission is:

1. Write to the buffer (the write might have happened to the cache, and not to the memory)

2. Clean the cache (transfer the cache contents to the memory, as the DMA engine takes data from the memory directly)

3. Enable DMA transfer

hope this helps.

Regards,

Sujith.

thanks for reply.

I am using the polled mode. and i config the MMU as following : 

/*
** Function to setup MMU. This function Maps three regions (1. DDR
** 2. OCMC and 3. Device memory) and enables MMU.
*/
static void MMUConfigAndEnable(void)
{
/*
** Define DDR memory region of AM335x. DDR can be configured as Normal
** memory with R/W access in user/privileged modes. The cache attributes
** specified here are,
** Inner - Write through, No Write Allocate
** Outer - Write Back, Write Allocate
*/
REGION regionDdr = {
MMU_PGTYPE_SECTION, START_ADDR_DDR, NUM_SECTIONS_DDR,
MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
MMU_CACHE_WT_NOWA),
MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
(unsigned int*)pageTable
};
/*
** Define OCMC RAM region of AM335x. Same Attributes of DDR region given.
*/
REGION regionOcmc = {
MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC,
MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
MMU_CACHE_WT_NOWA),
MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
(unsigned int*)pageTable
};

/*
** Define Device Memory Region. The region between OCMC and DDR is
** configured as device memory, with R/W access in user/privileged modes.
** Also, the region is marked 'Execute Never'.
*/
REGION regionDev = {
MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV,
MMU_MEMTYPE_DEVICE_SHAREABLE,
MMU_REGION_NON_SECURE,
MMU_AP_PRV_RW_USR_RW | MMU_SECTION_EXEC_NEVER,
(unsigned int*)pageTable
};

#if 0
/*
** Define NAND Region. The region is
** configured as device memory, with R/W access in user/privileged modes.
** Also, the region is marked 'Execute Never'.
*/
REGION regionNand = {
MMU_PGTYPE_SECTION, START_ADDR_NAND, NUM_SECTIONS_NAND,
MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
MMU_CACHE_WT_NOWA),
MMU_REGION_NON_SECURE,
MMU_AP_PRV_RW_USR_RW | MMU_SECTION_EXEC_NEVER,
(unsigned int*)pageTable
};
#endif

/* Initialize the page table and MMU */
MMUInit((unsigned int*)pageTable);

/* Map the defined regions */
MMUMemRegionMap(&regionDdr);
MMUMemRegionMap(&regionOcmc);
MMUMemRegionMap(&regionDev);
#if 0
MMUMemRegionMap(&regionNand);
#endif

/* Now Safe to enable MMU */
MMUEnable((unsigned int*)pageTable);
}

you can find that i set the memory as MMU_CACHE_WT_NOWA (Write through, No Write Allocate ) . and problem is still as above i told. 

Hi, 

If you are using polled mode, cache will not have an effect as you are putting the data directly into transmit register. But is it any timing issue as it works when you disable cache ? May be you can analyse the code in that way.

Regards,

Sujith.

I have tryed that disable all cache is working correctly for nand read/write using polled mode.