• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 98 subscribers
  • Views 668 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Some problem about uPP

xiang_li
Intellectual 935 points

Hi all,

I have some question when use uPP receive image data from FPGA.

My demo contain JPEG、EDMA、NetWork.

My question is following:

1) What is Underrun or Overflow (UOR) Event and How to distinguish  Underrun and Overflow, I think it is a FIFO level error. When it occur, I have make uPP  reset.

2)I have test many times, And I think uPP IDMA maybe be affected by EDMA or emac. It seems something make IDMA stop receive or make it so slowly. I have change

bus priority uPP and emac, make uPP higher, I think when use EDMA or send data to server will conflict with IDMA,and what something I haven`t note, or other suggest.

Thanks,

Li

  • 0
    TI__Genius 12065 points

    Li,

    1. The Overflow event is the inbound case (receiving) when the buffer is overflowed by the incoming data before they can be drained fast enough on the DMA side.

    Under-run is the outbound case (transmitting) when the buffer is under-run with the outgoing data before they can be filled fast enough on the DMA side. 

    So the combined event interrupt is indicating overflow or underrun will on your current DMA setup is for receiving or transmitting. 

    2. I think you may already notice section 2.6.3 System Tuning Tips in the UPP user's guide. You can try to increase the read burst size and line size to reduce the number of DMA events.

    For the priority, you can also try to reduce the EDMA3 TC priority in the queue priority register (QUEPRI) to adjust the system performance when you have EDMA transfer in the background with other masters transfer (e.g. UPP).

  • 0 in reply to Steven Ji
    Intellectual 935 points

    Hi Steven,

    Thanks for your good advise.

    I have change EDMA\UPP\EMAC priority. The number of UOR event  is reduce obviously. But still can occur.

    And I have another question about uPP.

    If I Software Reset uPP,  then it will sent a signal on WAIT pin? I use uPP on receive mode.

    Best Regards,

    Li

  • 0 in reply to xiang_li
    TI__Genius 12065 points

    Li,

    Please take a look at section 2.10 Emulation Considerations in uPP user guide. It says that uPP module (in receive mode) will assert WAIT signal if the three stop-running conditions are met, which includes EN bit =0 in the uPP peripheral control register (UPPCR). 

    If you do the software reset, the first step is to write EN=0 in UPPCR (section 2.7.1). So the software reset should send WAIT signal. Hope it is what you observed as well.

  • 0 in reply to Steven Ji
    Intellectual 935 points

    Hi Steven,

     Yes.You are right. The WAIT signal will be assert.

    Of course, it is not a big problem.

    The big problem is I can`t use uPP/EDMA/JPEG/EMAC together.

    My team need CLK 37.5MHz DDR mode(300MBps)receive capability.

    I have change bus priority: uPP 0, EDMA TC 3, EMAC 4.

    It seems very effective. UOR event lot less to occure, not none.

    I think as a port, it can perform perfectly. But use it in a project, We also need it can`t affect other peripheral.

    So Could you give me some other suggestion?

    Best Regards,

    Li

  • 0 in reply to xiang_li
    TI__Genius 12065 points

    Li,

    Are those peripherals accessing the same memory endpoint (such as L2 SRAM, MSMC SRAM or DDR) concurrently please?

    The uPP itself could handle 300MBps but in a competitive system scenario, the data rate of uPP may be limited as exactly what you have observed due to the system contention.

    The priority tuning is what we can try in the chip level. You may reduce the EDMA priority lower if necessary.

    The other things might be application design to see how to tune the timing and data traffic in the system. 

    Basically it will be good to prevent multiple masters accessing the same memory endpoint at the same time. And generally using the internal shared memory (L2/MSMC SRAM) could get better performance than accessing the external memory (DDR). 

    Hope you can find the balance point for your application.