ARM cache and shared memory L138 issue

Maxime Renaudet

Hi everyone,

There is a problem I haven't been able to solve and some of you might have encountered the same problem.

In my project, MMU is enabled on ARM (only cache, no memory protection) and the page table which describes all memory space is set to cache only external RAM. (0xC0000000 to 0xC8000000).

I only use section descriptor for the MMU page table, section descriptors are set to XXX00C12h for all sections but the external memory which is set to XXX00C1Ah. (Where XXX represent 12 adresses MSB). (bit 4 & 2 mus be '1', I only set C bit (bit 3) for external memory).

Anyways, when DSP writes into shared memory ARM doesn't see the changes unless it invalidates these cache lines. Is there any limations about handling shared memory caching ?

Thanks in advance for your answers.

Maxime

over 12 years ago

0 Maxime Renaudet over 12 years ago

Intellectual 510 points

It seems like i solved my problem afterall. In my own bootloader the shared memory is cached, then when my application is loaded I change the page table but the page table is cached into the Translation Lookaside Buffer (TLB), which needs to be invalidated after table change.

0 Renjith Thomas over 12 years ago

Guru 31670 points

Maxime,

I believe this is normal behavior. You'll need to invalidate the cached pages to see the updated values. The best way is to keep the shared buffers uncached.

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ARM cache and shared memory L138 issue