OMAP4430/60 MPU MMU CACE enable

Hi Iulian,

From what I understand, the MMU and cache configuration should be standard Cortex-A9 stuff.  It might be best to start off with the technical reference manuals directly from ARM:

http://arm.com/products/processors/cortex-a/cortex-a9.php

If you want to see how this works in practice, you can start with the Android code from omappedia.  Specifically, you'll want to look at the CPU-specific code in the x-loader such as x-loader/cpu/omap4/start.S, but that is just disabling the caches and MMU. 

Another interesting place to look in the Linux 3.0 kernel is: arch/arm/mach-omap2/sleep44xx.S, where the caches and MMU are disabled / enabled when going into / out of suspend mode.  There is also some code in arch/arm/boot/compressed/head.S that disables / enables the caches and MMU for ARMv7 (and other versions).  Note that all the above is using the GNU toolchain, so your assembler syntax may be different.

James Graves

Hi James,

4430 and 4460 has a cache controller named PL310, the standard mmu and cache controller is provided only for M3 and DSP(I understood how to make configuration for these controllers but PL310 is a mystery :) ), I look in some files in linux but is very confused because is not put all together, for example files for MMU to files for MMU , files for CACHE to files for CACHE.

But I will continue to lock in different distributions of linux.

I am disappointed because the ti developers can not provide a simple StarterWare for important modules, only for powering up and run at maximum performance, the rest of modules like uart, spi, twi lcd and others can be created by each user.

At this moment I created the support for:

• GPIO clock.
• Uart clock.
• Control module PinMux (almost all pins).
• GPIO 's modules.

But I used a linux MLO to initialize the PLL,s because the gel file for PandaBoard_ES can not support the rev B1 board.

Hi Iulian,

If what you need to know about the level 2 cache controller isn't covered by the ARM technical reference manual:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html

... you might also want to look at the processor initialization code for other Cortex-A9 chips.  It may be that one of the other popular A9 chips will have a better documented start-up routine.

Also, there were several different revisions for the cache controller in ARM's info center, but I couldn't easily find out which specific revision is used on the OMAP4460. So it would be good to investigate that too.

Good luck,

James

James Graves said:

Also, there were several different revisions for the cache controller in ARM's info center, but I couldn't easily find out which specific revision is used on the OMAP4460.

Section 4.1.2 "Features" in the OMAP4460 TRM indicates the following:

• PL310 L2 cache controller (revision r3p1-50rel0) with 1-MB cache size

Here's the corresponding info from OMAP4430:

• PL310 L2 cache controller (revision r2p0) with 1MB cache size

I create a asm file with this asm code :

;******************************************************************************

;****************************** Global Symbols*********************************
        .globl omap_smc_rom

;**************************** Text Section ************************************
        .text

; This source file is assembled for ARM instructions
        .state32
;*****************************************************************************
omap_smc_rom:
    push {r4-r11,lr}
    mov    r12,    r0
    mov    r0,    r1
    dsb
    isb
    dmb
    smc    #0
    pop {r4-r11,pc}
;
; End of the file
;
    .end

the example is tacked from x-loader, but hi give me these errors:

**** Build of configuration Debug for project SDK_Probe_OMAP4 ****

"C:\\ti\\ccsv5\\utils\\bin\\gmake" -k all
'Building file: ../main.c'
'Invoking: ARM Compiler'
"C:/ti/ccsv5/tools/compiler/arm_5.0.1/bin/armcl" --code_state=32 --abi=ti_arm9_abi -me -g --include_path="C:/ti/ccsv5/tools/compiler/arm_5.0.1/include" --include_path="C:/SDK/platform/omap4/driver/smc.asm" --include_path="C:/SDK/lib" --include_path="C:/SDK/platform/omap4/board/pandaboardes" --include_path="C:/SDK/platform/omap4" --rtti --gcc --diag_warning=225 --display_error_number --opt_for_cache -k --preproc_with_compile --preproc_dependency="main.pp"  "../main.c"
'Finished building: ../main.c'
' '
'Building file: ../smc.asm'
'Invoking: ARM Compiler'
"C:/ti/ccsv5/tools/compiler/arm_5.0.1/bin/armcl" --code_state=32 --abi=ti_arm9_abi -me -g --include_path="C:/ti/ccsv5/tools/compiler/arm_5.0.1/include" --include_path="C:/SDK/platform/omap4/driver/smc.asm" --include_path="C:/SDK/lib" --include_path="C:/SDK/platform/omap4/board/pandaboardes" --include_path="C:/SDK/platform/omap4" --rtti --gcc --diag_warning=225 --display_error_number --opt_for_cache -k --preproc_with_compile --preproc_dependency="smc.pp"  "../smc.asm"
"../smc.asm", ERROR!   at line 4: [E0002] Illegal mnemonic specified
5 Assembly Errors, No Assembly Warnings

>> Compilation failure
            .globl omap_smc_rom

"../smc.asm", ERROR!   at line 16: [E0002] Instruction only available in V7 and
                                           V6M0
        dsb

"../smc.asm", ERROR!   at line 17: [E0002] Instruction only available in V7 and
                                           V6M0
        isb

"../smc.asm", ERROR!   at line 18: [E0002] Instruction only available in V7 and
                                           V6M0
        dmb

"../smc.asm", ERROR!   at line 19: [E0002] Illegal mnemonic specified
        smc    #0


Errors in Source - Assembler Aborted
gmake: *** [smc.obj] Error 1
gmake: Target `all' not remade because of errors.

**** Build Finished ****

Know somebody what is the reason for these errors.

I observed that the CCS compiler can not recognise the smc instruction???????

I try from about three days to search a code that can be adapted to CCS but no result :(

At this moment I created drivers for uart gpio and i2c but the ram memory bandwidth is about 20MB/s :( ether the am335x from beaglebone has 60MB/s without cache enabled :(

If you need v7 instructions you can't use arm9 abi.  I think the eabi options are generally recommended.

I successfully compile the asm code at you suggestion, but without smc instruction :(

You have any idea how to compile the "smc" instruction?

The compiler report this:

**** Build of configuration Debug for project SDK_Probe_OMAP4 ****

"C:\\ti\\ccsv5\\utils\\bin\\gmake" -k all
'Building file: ../main.c'
'Invoking: ARM Compiler'
"C:/ti/ccsv5/tools/compiler/arm_5.0.1/bin/armcl" -mv7A8 --code_state=32 --abi=eabi -me -g --include_path="C:/ti/ccsv5/tools/compiler/arm_5.0.1/include" --include_path="C:/SDK/platform/omap4/driver/smc.asm" --include_path="C:/SDK/lib" --include_path="C:/SDK/platform/omap4/board/pandaboardes" --include_path="C:/SDK/platform/omap4" --rtti --gcc --diag_warning=225 --display_error_number --opt_for_cache -k --preproc_with_compile --preproc_dependency="main.pp"  "../main.c"
'Finished building: ../main.c'
' '
'Building file: ../smc.asm'
'Invoking: ARM Compiler'
"C:/ti/ccsv5/tools/compiler/arm_5.0.1/bin/armcl" -mv7A8 --code_state=32 --abi=eabi -me -g --include_path="C:/ti/ccsv5/tools/compiler/arm_5.0.1/include" --include_path="C:/SDK/platform/omap4/driver/smc.asm" --include_path="C:/SDK/lib" --include_path="C:/SDK/platform/omap4/board/pandaboardes" --include_path="C:/SDK/platform/omap4" --rtti --gcc --diag_warning=225 --display_error_number --opt_for_cache -k --preproc_with_compile --preproc_dependency="smc.pp"  "../smc.asm"
"../smc.asm", ERROR!   at line 20: [E0002] Illegal mnemonic specified
1 Assembly Error, No Assembly Warnings

>> Compilation failure
        smc    #0


Errors in Source - Assembler Aborted
gmake: *** [smc.obj] Error 1
gmake: Target `all' not remade because of errors.

**** Build Finished ****

Try SMI #0.

I tried SMI #0 but at execution hi go to abort.

First go to

00030004:   E59FF018 LDR             PC, 0x30024

from here to

4030d004:   E59FF018 LDR             PC, 0x4030D024

from here to

00030080:   EAFFFFFE B               0x30080

and here remain in infinite loop.

Hi Brad,

Do you have an example of how to setup the a GPMC address to be used as cache?  Currently, I have looked at all the TRMs and still lost.

preferably in C, but if it can only be done in assembly, and example would be extremely helpful.

This is for 4430 on the pandaboard, running u-boot.

thanks,

Vincent

Vince Yee said:

Do you have an example of how to setup the a GPMC address to be used as cache?

Do you mean how to set it up as cacheable memory?  I don't have any code examples of that.  However, the appropriate documentation would be the ARM Architecture Reference Manual Section B3.8 "Memory region attributes".  This is part of the MMU page table configuration.  You might look at the linux code for arch/arm/mm/mmu.c.

Yes, sample code for how to setup as cachable memory.  I've looked at the linux code and found I am missing a step to setup the address location into the cache controller.  It is working now.

thanks.