• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 542 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Reduce C6678 clock rate

Daisuke Maeda
Guru 20205 points

Our customer wants to reduce the clock rate to reduce the power consumption.

They use the 1250MHz device.
I guess that the SYSCLK1 can be reduced to 800MHz, 1000MHz, 1200MHz.
Can other clock frequency be used for SYSCLK1?

What is the minimum clock frequency for each clock (SYSCLKn, DDR3 PLLOUT, PASS PLLOUT)?

Best regards,

Daisuke

 

  • 0
    TI__Mastermind 30825 points

    The min supported are what's documented in the Data Manual, that's 800MHz for SYSCLK, PASS has a fixed requirement in the Data Manual, and DDR3 would be to the min spec of DDR3. 

    That said, this is only going to reduce the activity power consumption.  It's not necessarily going to have a significant overall reduction in power consumption.

    Please note that taking a 1250MHz device and running it at 1000MHz is not going to get you to the power numbers of the 1000MHz unit in the power spreadsheet.  The biasing and process needed to be able to achieve 1250MHz results in a higher leakage current and thus higher baseline curve.  This curve would not change when reducing the frequency.  Only the Activity power would be impacted by reducing the frequency of a given unit.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Guru 20205 points

    Hi Chad,

    Thank you for your reply.

    Best regards,

    Daisuke