Hello,
In our application we use the L3 memory to communicate between the DSP and PRUSS within the OMAP-L138 SOC. The DSP writes a few words of data to the L3 Shared memory, then signals a host interrupt in the PRU interrupt controller to signal the PRU that it has some operation to perform. Generally this works very well and we don't have problems. However, in a longevity test we have encountered situations where the PRU is signalled and is trying to process stale data. Our data indicates to us that writes to L3 were somehow delayed, or at least not complete by the end of the CPU write instruction. We are wondering if this is true and how we can enforce that writes to L3 are complete before we signal the PRU host interrupt. BTW, L3 is not cached by the DSP or ARM.
Thanks,
-David