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DM8148 EVM gel file DMtimer regsiter base addresses

TIDR
Genius 9345 points

I'm investigating an issue with dmtimer setting on DM8148 EVM and as a result looked through the DM8148 gel file. The gel file I have shows the following:

#define DMTIMER0_BASE_ADDR     0x4802C000  

#define DMTIMER1_BASE_ADDR     0x4802E000  

#define DMTIMER2_BASE_ADDR     0x48040000  

#define DMTIMER3_BASE_ADDR     0x48042000  

#define DMTIMER4_BASE_ADDR     0x48044000  

#define DMTIMER5_BASE_ADDR     0x48046000  

#define DMTIMER6_BASE_ADDR     0x48048000

 #define DMTIMER7_BASE_ADDR     0x4804A000

 

However, the DM8148 datasheet on the web (Sept 2012) version shows the following in table 2-6:

0x4802_C000 0x4802_DFFF 0x0802_C000 0x0802_DFFF 8KB Reserved

0x4802_E000 0x4802_EFFF 0x0802_E000 0x0802_EFFF 4KB TIMER1 Peripheral Registers

0x4802_F000 0x4802_FFFF 0x0802_F000 0x0802_FFFF 4KB TIMER1 Support Registers

 

The gel file numbers the timers as 0-7 whereas the datasheet uses 1-8 however timer0 address of 0x4802C000 is reserved so this is not going to work.

 

Rgds

-Dipa-

 

  • 0
    TI__Genius 15310 points

    Hi Dipa,

    The Gel file does not use any of DMTIMERx_BASE_ADDR defined so it must be an overlook when Mistral porting the Gel file from other project.  We will fix the Gel file by removing them.  . 

    In the future, the DS should always cheat as a superset over TRM and SW.

    BR,

    Viet